SN74ALVCH16827: Buffer Output logic state when input is high and supply voltage is not connected.

Saikumar Kanikatla

Part Number: SN74ALVCH16827

To buffer a LVTTL signal to FPGA I am using this TI buffer SN74ALVCH16827DGGR.The buffer IC is placed on a FMC based IO card mated to a ZYNQ mother card. The problem I am facing here is when an input signal is applied to the buffer IC, there is an output signal even when there is no power supply to this IC. The output enable signals are connected to PCB GND. I want to avoid this as it may damage the FPGA. Can someone suggest me with a solution?

over 3 years ago

0 Rami Mooti1 over 3 years ago

TI__Mastermind 23673 points

Saikumar,

When the device is powered down, are you pulling the /OE pins high? This helps ensure that the device is in a high impedance state while the device is powered down/up.

Thanks,
Rami

0 Saikumar Kanikatla over 3 years ago in reply to Rami Mooti1

Prodigy 40 points

I have enabled the IC by connecting the enable pins directly to ground, not provided any pull-ups on #OE pins.

+1 Rami Mooti1 over 3 years ago in reply to Saikumar Kanikatla

TI__Mastermind 23673 points

Saikumar,

This device doesn't have the 'partial power down' feature. If you want to use this device, you'll need to hold the /OE pin high until it's powered up to ensure a high-z state.
There are 20-channel devices with this feature, such as the SN74ALVTH16827 which will hold the buffer in a high-Z state while the Vcc is between 0 and 1.2V.

Thanks,
Rami

0 Saikumar Kanikatla over 3 years ago in reply to Rami Mooti1

Prodigy 40 points

Rami,

Thank you. I have ordered the part SN74ALVTH16827. Will test the circuitry once I receive the IC.

0 Saikumar Kanikatla over 3 years ago in reply to Rami Mooti1

Prodigy 40 points

This Partial power-down feature helped, But I got another issue with this IC. When I am applying a signal input >1.7V, the output is stuck at 1.65V even when the input is increased to 3.3V. As this IC is a buffer the output should be the same as the input. I am a little confused. Can someone guide me through this?

0 Clemens Ladisch over 3 years ago in reply to Saikumar Kanikatla

Guru 244020 points

This is a digital buffer, which is either low or high; the output voltage is determined by the supply voltage.

0 Saikumar Kanikatla over 3 years ago in reply to Clemens Ladisch

Prodigy 40 points

I am supplying the IC with a positive 3.3V. As per the datasheet, VOH should be VCC-0.2. But in my case, the output high voltage is fixed at 1.65V. I have not added any passive circuitry to the above-mentioned IC except the decaps. Connected the output enable pins to board ground. Is there anything I am missing in my design. Kindly suggest. Thank You.

0 Clemens Ladisch over 3 years ago in reply to Saikumar Kanikatla

Guru 244020 points

Either the supply voltage is not what you assume it is, or the output is shorted to another output that drives low.

0 Rami Mooti1 over 3 years ago in reply to Saikumar Kanikatla

TI__Mastermind 23673 points

Could you provide a schematic of your setup? A rough drawing will do just so I can see if there's anything going on here that you may be missing.

Thanks,
Rami

0 Saikumar Kanikatla over 3 years ago in reply to Rami Mooti1

Prodigy 40 points

I am attaching the schematic for reference. The Buffer part is changed from SN74ALVCH16827 to SN74ALVTH16827 to achieve the partial-power-down feature. I have measured the power supply using a multimeter and it is 3.3V.

Schematic

0 Saikumar Kanikatla over 3 years ago in reply to Clemens Ladisch

Prodigy 40 points

The supply voltage was good. As you said, the output pin is shorted to another output, which was not observed in the visual inspection. Slight touch-up and Now it is working as expected. Thank you.

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SN74ALVCH16827: Buffer Output logic state when input is high and supply voltage is not connected.