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SN74LVC1G11-EP: Follow up questions on this part

Part Number: SN74LVC1G11-EP

Hi again,

I have some follow up questions on this part.

Here they are:

  • What is the detailed over voltage protection mechanism ?
  • Does this protection limit both the input current and the input voltage ? How ?
  • We may have continuous operating modes where we send a +15V voltage source in series with a 10kOhm to the SN74LVC1G11-EP input. Is it OK?
  • We may have continuous operating modes where we send a -15V voltage source in series with a 10kOhm to the SN74LVC1G11-EP input. Is it OK?

Thanks very much for your help.

Best regards,

Annaïs

  • There is not really a "mechanism" that protects against overvoltage; when there is a voltage higher than VCC, the device is not affected because there is no path where current could flow into the device. The current is always zero; the absence of the ESD diode from the input pin to VCC is the protection.

    The absolute maximum ratings allow a −15 V voltage as long as the diode current is limited to less than 50 mA. The 10 kΩ resistor is enough for that.

    However, when there is a positive voltage, no current flows, until the isolation breaks down at voltages above 6.5 V. Higher voltages are not allowed, under any circumstances. The LVC overvoltage tolerance is designed for logic voltages up to 5 V, not for higher analog signals.

    You have to add some external mechanism to clamp higher voltages to about 5 V.

  • Thanks Clemens.
    Annais,
    I concur with Clemens reply.
    For devices with an IIK or IOK specification, the absolute max limits can be exceeded for the voltage if the IIK or IOK limit is adhered to.
    Note, for this device the IIK spec only applies when Vi is less than 0v (for same reason as Clemens mentions).

    Regards,
    Wade