Other Parts Discussed in Thread: SN74HCS74
Hi team,
on data sheet Figure 5, there is a RC delay circuit at CLR pin diagram. Is there any constraint for RC circuit design? If RC delay time is longer or short, does it impact IC reset function? or I need care of reset threshold voltage only?
Design target: output Q is able to change state from “low” to “high” once a reset signal (Low -> high) from system
- When power on, no signal, action 1, Q=Low is target.
So a RC circuit is used to delay CLR pin from Low state then change to high state
- Once 3.3V is ready, then PRE= CLR =D = High, then CLK has rising edge to make output Q change to “high” from “Low”
