RX BUFFER PROBLEM

Not sure I understand the problem. When you say that there is problem with the development board, are you referring to TrxEB running SmartRF Studio? I think Studio  (in normal mode will not display the length byte, i.e. the first byte after sync word).

since you want to use foxed packet length mode you should do this on Studio also (use the advanced option in the bottom.) When you select fix packet length mode you will see all received bytes after the sync word (44).

BR

Siri

No i have not problem with SmartRF studio , TrxEB TX and RX board work ok . I want to explain that on my side use develop board FR5739 and CC112xEM .

Sending data from FR5739 work fine , have receive on SmartRF  .. RX and receive every byte  but wen send data from SmartRF  TX, FR5739 receive packet but no have first byte . But smartRF RX normaly receive all bytes  include first byte like on TX side .

I try packet config registers on FR5739 side but have no result , all time get data and no first byte ...

To be able to help you we will need access to your register settings and the receiver code. It would also be helt ful to get info on what interrupt you are using etc.

BR

Siri

Hi Siri

This is actual detail registers ,SPI receive and interrupts samples :

static const char wmbus_4800_N1[]=
{
        0XB0,//IOCFG3 GPIO3 IO Pin Configuration
        0X06,//IOCFG2 GPIO2 IO Pin Configuration
        0XB0,//IOCFG1 GPIO1 IO Pin Configuration
        0XB0,//IOCFG0 GPIO0 IO Pin Configuration 0XB0 0X40
        0XAA,//SYNC3 Sync Word Configuration [31:24]
        0XAA,//SYNC2 Sync Word Configuration [23:16]
        0XF6,//SYNC1 Sync Word Configuration [15:8]
        0X8D,//SYNC0 Sync Word Configuration [7:0]
        0X08,//SYNC_CFG1 Sync Word Detection Configuration
        0X0B,//SYNC_CFG0 Sync Word Length Configuration
        0X3A,//DEVIATION_M Frequency Deviation Configuration
        0X09,//MODCFG_DEV_E Modulation Format and Frequency Deviation Configuration
        0X1C,//DCFILT_CFG Digital DC Removal Configuration
        0X18,//PREAMBLE_CFG1 Preamble Length Configuration
        0X2A,//PREAMBLE_CFG0
        0X40,//FREQ_IF_CFG RX Mixer Frequency Configuration
        0XC6,//IQIC Digital Image Channel Compensation Configuration
        0X10,//CHAN_BW Channel Filter Configuration
        0X46,//MDMCFG1 General Modem Parameter Configuration
        0X05,//MDMCFG0 General Modem Parameter Configuration
        0X63,//DRATE2 Data Rate Configuration Exponent and Mantissa [19:16]
        0XA9,//DRATE1 Data Rate Configuration Mantissa [15:8]
        0X2A,//DRATE0 Data Rate Configuration Mantissa [7:0]
        0X20,//AGC_REF AGC Reference Level Configuration
        0X19,//AGC_CS_THR Carrier Sense Threshold Configuration
        0X00,//AGC_GAIN_ADJUST RSSI Offset Configuration
        0X91,//AGC_CFG3 AGC Configuration
        0X20,//AGC_CFG2 AGC Configuration
        0XA9,//AGC_CFG1 AGC Configuration
        0XCF,//AGC_CFG0 AGC Configuration
        0X78,//FIFO_CFG FIFO Configuration
        0X25,//DEV_ADDR Device Address Configuration
        0X03,//SETTLING_CFG Frequency Synthesizer Calibration and Settling Configuration
        0X1A,//FS_CFG Frequency Synthesizer Configuration
        0X08,//WOR_CFG1 eWOR Configuration, Reg 1
        0X21,//WOR_CFG0 eWOR Configuration, Reg 0
        0X00,//WOR_EVENT0_MSB Event 0 Configuration
        0X00,//WOR_EVENT0_LSB Event 0 Configuration
        0X04,//PKT_CFG2 Packet Configuration, Reg 2 0X04
        0X01,//PKT_CFG1 Packet Configuration, Reg 1 0X01
        0X00,//PKT_CFG0 Packet Configuration, Reg 0 0X00
        0X0F,//RFEND_CFG1 RFEND Configuration, Reg 1
        0X00,//RFEND_CFG0 RFEND Configuration, Reg 0
        0X7F,//PA_CFG2 Power Amplifier Configuration, Reg 2
        0X56,//PA_CFG1 Power Amplifier Configuration, Reg 1
        0X7E,//PA_CFG0 Power Amplifier Configuration, Reg 0
        0X2C,// PKT_LEN Packet Length Configuration
          //exteded
        0X00,//IF_MIX_CFG IF Mix Configuration
        0X22,//FREQOFF_CFG Frequency Offset Correction Configuration
        0X0B,//TOC_CFG Timing Offset Correction Configuration
        0X00,//MARC_SPARE MARC Spare
        0X00,//ECG_CFG External Clock Frequency Configuration
        0X00,//SOFT_TX_DATA_CFG Soft TX Data Configuration
        0X01,//EXT_CTRL External Control Configuration
        0X00,//RCCAL_FINE RC Oscillator Calibration (fine)
        0X00,//RCCAL_COARSE RC Oscillator Calibration (coarse)
        0X00,//RCCAL_OFFSET RC Oscillator Calibration Clock Offset
        0X00,//FREQOFF1 Frequency Offset (MSB)
        0X00,//FREQOFF0 Frequency Offset (LSB)
        0X69,//FREQ2 Frequency Configuration [23:16]
        0XE1,//FREQ1 Frequency Configuration [15:8]
        0X00,//FREQ0 Frequency Configuration [7:0]
        0X02,//IF_ADC2 Analog to Digital Converter Configuration, Reg 2
        0XA6,//IF_ADC1 Analog to Digital Converter Configuration, Reg 1
        0X04,//IF_ADC0 Analog to Digital Converter Configuration, Reg 0
        0X00,//FS_DIG1
        0X5F,//FS_DIG0
        0X00,//FS_CAL3
        0X20,//FS_CAL2
        0X40,//FS_CAL1
        0X0E,//FS_CAL0
        0X29,//FS_CHP Charge Pump Configuration 0X27 za RX   , 0X29 za TX
        0X03,//FS_DIVTWO Divide by 2
        0X00,//FS_DSM1 Digital Synthesizer Module Configuration, Reg 1
        0X33,//FS_DSM0 Digital Synthesizer Module Configuration, Reg 0
        0XFF,//FS_DVC1 Divider Chain Configuration, Reg 1
        0X17,//FS_DVC0 Divider Chain Configuration, Reg 0
        0X00,//FS_LBI Local Bias Configuration
        0X50,//FS_PFD Phase Frequency Detector Configuration
        0X6E,//FS_PRE Prescaler Configuration
        0X14,//FS_REG_DIV_CML
        0XAC,//FS_SPARE
        0X10,//FS_VCO4 VCO Configuration, Reg 4  0X11 za RX , 0X10 za TX
        0X00,//FS_VCO3 VCO Configuration, Reg 3
        0X36,//FS_VCO2 VCO Configuration, Reg 2 0X11 za RX , 0X36 za TX
        0X9C,//FS_VCO1 VCO Configuration, Reg 1
        0XB4,//FS_VCO0 VCO Configuration, Reg 0
        0X00,//GBIAS6 Global Bias Configuration, Reg 6
        0X02,//GBIAS5 Global Bias Configuration, Reg 5
        0X00,//GBIAS4 Global Bias Configuration, Reg 4
        0X00,//GBIAS3 Global Bias Configuration, Reg 3
        0X10,//GBIAS2 Global Bias Configuration, Reg 2
        0X00,//GBIAS1 Global Bias Configuration, Reg 1
        0X00,//GBIAS0 Global Bias Configuration, Reg 0
        0X01,//IFAMP Intermediate Frequency Amplifier Configuration
        0X01,//LNA Low Noise Amplifier Configuration
        0X01,//RXMIX RX Mixer Configuration
        0X0E,//XOSC5 Crystal Oscillator Configuration, Reg 5
        0XA0,//XOSC4 Crystal Oscillator Configuration, Reg 4
        0X03,//XOSC3 Crystal Oscillator Configuration, Reg 3
        0X04,//XOSC2 Crystal Oscillator Configuration, Reg 2
        0X03,//XOSC1 Crystal Oscillator Configuration, Reg 1
        0X00,//XOSC0 Crystal Oscillator Configuration, Reg 0
        0X00,//ANALOG_SPARE
        0X00,//PA_CFG3 Power Amplifier Configuration, Reg 3
        0X00,//IRQ0M IRQ0 Mask Configuration
        0X00,//IRQ0F IRQ0 Flag
        0X00,//fali PA_CFG3
        0X00,//WOR_TIME1 eWOR Timer Status (MSB)
        0X00,//WOR_TIME0 eWOR Timer Status (LSB)
        0X00,//WOR_CAPTURE1 eWOR Timer Capture (MSB)
        0X00,//WOR_CAPTURE0 eWOR Timer Capture (LSB)
        0X00,//BIST MARC BIST
        0X17,//DCFILTOFFSET_I1 DC Filter Offset I (MSB) 0XF5 za RX , 0X17 za TX
        0X76,//DCFILTOFFSET_I0 DC Filter Offset I (LSB) 0XA3 za RX , 0X76 za TX
        0X06,//DCFILTOFFSET_Q1 DC Filter Offset Q (MSB) 0X0C za RX , 0X06 za TX
        0XD0,//DCFILTOFFSET_Q0 DC Filter Offset Q (LSB) 0X0C za RX , 0XD0 za TX
        0XFC,//IQIE_I1 IQ Imbalance Value I (MSB) 0XF3 za RX , 0XFC za TX
        0X2E,//IQIE_I0 IQ Imbalance Value I (LSB) 0X38 za RX , 0X2E za TX
        0X05,//IQIE_Q1 IQ Imbalance Value Q (MSB) 0XF6 za RX , 0X05 za TX
        0X58,//IQIE_Q0 IQ Imbalance Value Q (LSB) 0XB7 za RX , 0X58 za TX
        0X80,//RSSI1 Received Signal Strength Indicator (MSB)
        0X00,//RSSI0 Received Signal Strength Indicator (LSB)
        0X41,//MARCSTATE MARC State
        0X00,//LQI_VAL Link Quality Indicator Value
        0XFF,//PQT_SYNC_ERR Preamble and Sync Word Error
        0X00,//DEM_STATUS Demodulator Status
        0X00,//FREQOFF_EST1 Frequency Offset Estimate (MSB)
        0X00,//FREQOFF_EST0 Frequency Offset Estimate (LSB)
        0X00,//AGC_GAIN3 AGC Gain, Reg 3
        0XD1,//AGC_GAIN2 AGC Gain, Reg 2
        0X1A,//AGC_GAIN1 AGC Gain, Reg 1
        0X3F,//AGC_GAIN0 AGC Gain, Reg 0
        0X00,//SOFT_RX_DATA_OUT Soft Decision Symbol Data
        0X00,//SOFT_TX_DATA_IN Soft TX Data Input Register
        0X30,//ASK_SOFT_RX_DATA AGC ASK Soft Decision Output
        0X7F,//RNDGEN Random Number Value
        0X00,//MAGN2 Signal Magnitude after CORDIC [16]
        0X00,//MAGN1 Signal Magnitude after CORDIC [15:8]
        0X00,//MAGN0 Signal Magnitude after CORDIC [7:0]
        0X00,//ANG1 Signal Angular after CORDIC [9:8]
        0X00,//ANG0 Signal Angular after CORDIC [7:0]
        0X08,//CHFILT_I2 Channel Filter Data Real Part [18:16]
        0X00,//CHFILT_I1 Channel Filter Data Real Part [15:8]
        0X00,//CHFILT_I0 Channel Filter Data Real Part [7:0]
        0X00,//CHFILT_Q2 Channel Filter Data Imaginary Part [18:16]
        0X00,//CHFILT_Q1 Channel Filter Data Imaginary Part [15:8]
        0X00,//CHFILT_Q0 Channel Filter Data Imaginary Part [7:0]
        0X00,//GPIO_STATUS GPIO Status
        0X01,//FSCAL_CTRL
        0X00,//PHASE_ADJUST
        0X48,//PARTNUMBER Part Number
        0X21,//PARTVERSION Part Revision
        0X00,//SERIAL_STATUS Serial Status
        0X10,//RX_STATUS RX Status
        0X00,//TX_STATUS TX Status
        0X00,//MARC_STATUS1 MARC Status, Reg 1
        0X00,//MARC_STATUS0 MARC Status, Reg 0
        0X00,//PA_IFAMP_TEST
        0X00,//FSRF_TEST
        0X00,//PRE_TEST
        0X00,//PRE_OVR
        0X00,//ADC_TEST ADC Test
        0X0B,//DVC_TEST DVC Test
        0X40,//ATEST
        0X00,//ATEST_LVDS
        0X00,//ATEST_MODE
        0X3C,//XOSC_TEST1
        0X00,//XOSC_TEST0
        0X00,//RXFIRST RX FIFO Pointer (first entry)
        0X00,//TXFIRST TX FIFO Pointer (first entry)
        0X00,//RXLAST RX FIFO Pointer (last entry)
        0X00,//TXLAST TX FIFO Pointer (last entry)
        0X00,//NUM_TXBYTES TX FIFO Status (occupied entries)
        0X00,//NUM_RXBYTES RX FIFO Status (occupied entries)
        0X0F,//FIFO_NUM_TXBYTES TX FIFO Status (free entries)
        0X00,//FIFO_NUM_RXBYTES RX FIFO Status (available bytes)
};

main(){

...

while()

{

if(SPI_RX)
    {

        SPI_RX=0;

        spi_count=SPIReadReg(PKT_LEN);//SPIReadReg(NUM_RXBYTES);
        sprintf((char*)tx_buffer,"number of rx=%d \r\n",(int)spi_count);//read adr
        send_len((const char*)tx_buffer,strlen((const char*)tx_buffer));
        if(spi_count>0X80)spi_count=0X80;
        SPIReadBurstReg (FIFO_DMA+0X80 , SPI_rx_buffer , spi_count);//FIFO_DMA
         status=SPIStrobe(SNOP);// back in rx
           sprintf((char*)tx_buffer,"status =0X%x \r\nreceive hex: \r\n",(int)status);//read adr
          send_len((const char*)tx_buffer,strlen((const char*)tx_buffer));

          for (i=0;i < spi_count;i++)
          {
              sprintf((char*)tx_buffer,"0X%x ",(int)SPI_rx_buffer[i]);
              send_len((const char*)tx_buffer,strlen((const char*)tx_buffer));
          }
          send_len("\r\n",2);
          spi_count=0;
          status=SPIStrobe(SIDLE);
          status=SPIStrobe(SFRX);
          status=SPIStrobe(SRX);
    }

}

}

//******************************************************************************
//
//This is the PORT2_VECTOR interrupt vector service routine
//
//******************************************************************************
#pragma vector=PORT2_VECTOR
__interrupt void Port_2 (void)
{
    GPIO_clearInterruptFlag (GPIO_PORT_P2,GPIO_PIN3);
    SPI_RX=1;
    GPIO_toggleOutputOnPin(GPIO_PORT_P3,GPIO_PIN6);//turn led on/off
}

//******************************************************************************
//
//This is the USCI_B0_VECTOR SPI interrupt vector service routine
//
//******************************************************************************

#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR (void)
{
    switch (__even_in_range(UCB0IV,4)){
        //Vector 2 - RXIFG
        case 2:
            //USCI_A0 TX buffer ready?
            //while (!EUSCI_B_SPI_getInterruptStatus(EUSCI_B0_BASE,
            //           EUSCI_B_SPI_TRANSMIT_INTERRUPT)) ;

            SPI_RXData = EUSCI_B_SPI_receiveData(EUSCI_B0_BASE);
            SPI_RXstatus=1;
            break;
        default: break;
    }
}

//******************************************************************************
// @fn          SPIReadBurstReg
// @brief       Reads multiple configuration registers, the first register being
//              at specified address; values read are stored sequentially from
//              start of buffer until specified number of registers have been
//              read
// @param       char addr     Address to start of registers to be read
//              char *buffer  Values read from registers
//              char count    Number of register to be read
// @return      none
//******************************************************************************

//******************************************************************************

// this is read burst register  from CC1120

//******************************************************************************
void SPIReadBurstReg(unsigned int addr, unsigned char *buffer, unsigned char count)
{
  unsigned char i;

  //TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN;        // /CS enable
  GPIO_setOutputLowOnPin(GPIO_PORT_P1,GPIO_PIN3);
  if (addr>>8==0X2F || addr>>8==0X3E || addr>>8==0X3F ||addr>>8==0XBE )
   {
      //------------------------tx extended read
           while (!(UCB0IFG&UCTXIFG));// Wait for TXBUF ready
          if (addr>>8 ==0X2F)
              UCB0TXBUF = 0X2F + CCRF_REGRD;
          else if(addr>>8 ==0X3E)
              UCB0TXBUF = 0X3E + CCRF_REGRD;
          else if(addr>>8 ==0X3F)
              UCB0TXBUF = 0X3F + CCRF_REGRD;
           while (!(UCB0IFG&UCTXIFG));               // Wait for TXBUF ready
           UCB0TXBUF =(unsigned char) addr&0XFF;  // write addres

           while (!(UCB0IFG&UCTXIFG));               // Wait for TXBUF ready
           UCB0TXBUF =0;

           // Addr byte is now being TX'ed, with dummy byte to follow immediately after
           UCB0IFG &= ~UCRXIFG;                      // Clear flag
           while (!(UCB0IFG&UCRXIFG));               // Wait for end of addr byte TX
           buffer[0] = UCB0RXBUF;                    // dummy read
           // First data byte now in RXBUF
           for (i = 0; i < (count); i++)
           {
             UCB0TXBUF = 0;                          // Initiate next data TX, meanwhile..
             while (!(UCB0IFG&UCRXIFG));             // Wait for RX to complete
             buffer[i] = UCB0RXBUF;                  // Store data from last data RX
           }
           //buffer[count-1] = UCB0RXBUF;              // Store last RX byte in buffer

           GPIO_setOutputHighOnPin(GPIO_PORT_P1,GPIO_PIN3);
           return;
   }
  while (!(UCB0IFG&UCTXIFG));               // Wait for TXBUF ready
  UCB0TXBUF = (unsigned char)(addr + CCRF_REGRD);          // Send address
  while (UCB0STAT & UCBUSY);                // Wait for TX complete
  UCB0TXBUF = 0;                            // Dummy write to read 1st data byte
  // Addr byte is now being TX'ed, with dummy byte to follow immediately after
  UCB0IFG &= ~UCRXIFG;                      // Clear flag
  while (!(UCB0IFG&UCRXIFG));               // Wait for end of addr byte TX
  //buffer[0] = UCB0RXBUF;                    // dummy read
  // First data byte now in RXBUF
  for (i = 0; i < (count); i++)
  {
    UCB0TXBUF = 0;                          // Initiate next data TX, meanwhile..
    buffer[i] = UCB0RXBUF;                  // Store data from last data RX
    while (!(UCB0IFG&UCRXIFG));             // Wait for RX to complete
  }
  //buffer[count-1] = UCB0RXBUF;              // Store last RX byte in buffer
  GPIO_setOutputHighOnPin(GPIO_PORT_P1,GPIO_PIN3);
}

//******************************************************************************
// @fn          SPIStrobe
// @brief       Writes to the strobe at specified address
// @param       char strobe  Strobe to be written to a register
// @return      char strobe  Strobe returned from register
//******************************************************************************
unsigned char SPIStrobe(unsigned char strobe)
{
  unsigned char status;

  // Check for valid strobe command
  if((strobe == 0xBD) || ((strobe > CCRF_SRES) && (strobe < CCRF_SNOP)))
  {
    //TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN;      // /CS enable
    GPIO_setOutputLowOnPin(GPIO_PORT_P1,GPIO_PIN3);
    // send_len("TX step 1\r\n",11);
    while (!(UCB0IFG&UCTXIFG));             // Wait for TXBUF ready
    UCB0TXBUF = strobe;                     // Send strobe
    // Strobe addr is now being TX'ed
    //send_len("TX step 2\r\n",11);
    while (!(UCB0IFG&UCTXIFG));             // Wait for TXBUF ready
    UCB0TXBUF = (strobe + CCRF_REGRD);      // Send address
    //send_len("TX step 3\r\n",11);
    while (!(UCB0IFG&UCTXIFG));             // Wait for TXBUF ready
    UCB0TXBUF = 0;                          // Dummy write so we can read data
    //send_len("TX step 4\r\n",11);
    while (UCB0STAT & UCBUSY);              // Wait for TX to complete
    status = UCB0RXBUF;                     // Read data
    //TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;       // /CS disable
    //send_len("TX step 5\r\n",11);
    GPIO_setOutputHighOnPin(GPIO_PORT_P1,GPIO_PIN3);
  }

  return status;
}

best regards

Kresimir