Other Parts Discussed in Thread: HALCOGEN
Hi Team
Hope you are doing good.
I have a very strange problem which i m not able to solve. I would be very grateful to you if you could please help me solving the same quickly as it is really very urgent for the project.
I have implemented a SPI slave DMA interrupt on RM44L520.
Everytime the master sends the data, the interrupt is triggered which is what i expected.
The problem is... when the master is not sending any data, the slave is stuck at following statement and never exits from here. i am clueless why is this happening.
(*pf_irqFunc)(); /* Execute interrupt routine */
This statement is part of following function
void irqHandler(uint32_t u32VectorIrqIndex) { t_isrFuncPTR pf_irqFunc = NULL; /* Assign Null address */ /* Check IrqVector Range */ if ((u32VectorIrqIndex > (uint32_t)0U) && (u32VectorIrqIndex <= U32_VIM_CHAN_MAX) /* index is valid */) { pf_irqFunc = vimRAM->ISR[u32VectorIrqIndex]; /* Read IRQ Interrupt Vector */ /* Save VIM REQENASET[0,1,2,3] Registers for later restore */ uint32 u32BckupREQMASKSET0 = vimREG->REQMASKSET0; uint32 u32BckupREQMASKSET1 = vimREG->REQMASKSET1; uint32 u32BckupREQMASKSET2 = vimREG->REQMASKSET2; uint32 u32BckupREQMASKSET3 = vimREG->REQMASKSET3; /* Mask out lower priority IRQs depending on IRQ index */ if(U32_VIM_CHAN3_OFFSET < u32VectorIrqIndex) /* Channel 97-127*/ { vimREG->REQMASKCLR3 = ((U32_REG_CLRMASK << (u32VectorIrqIndex - 97U)) & (~vimREG->FIRQPR3)); /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ vimREG->REQMASKCLR3 = vimREG->REQMASKCLR3; } else if (U32_VIM_CHAN2_OFFSET < u32VectorIrqIndex) /* Channel 64-96 */ { vimREG->REQMASKCLR2 = ((U32_REG_CLRMASK << (U32_CHAN_REG2_OFFSET(u32VectorIrqIndex))) & (~vimREG->FIRQPR2)); vimREG->REQMASKCLR3 = ( U32_REG_CLRMASK & (~vimREG->FIRQPR3)); /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ vimREG->REQMASKCLR3 = vimREG->REQMASKCLR3; vimREG->REQMASKCLR2 = vimREG->REQMASKCLR2; } else if (U32_VIM_CHAN1_OFFSET < u32VectorIrqIndex) /* Channel 32-63 */ { vimREG->REQMASKCLR1 = ((U32_REG_CLRMASK << (U32_CHAN_REG1_OFFSET(u32VectorIrqIndex))) & (~vimREG->FIRQPR1)); vimREG->REQMASKCLR2 = ( U32_REG_CLRMASK & (~vimREG->FIRQPR2)); vimREG->REQMASKCLR3 = ( U32_REG_CLRMASK & (~vimREG->FIRQPR3)); /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ vimREG->REQMASKCLR3 = vimREG->REQMASKCLR3; vimREG->REQMASKCLR2 = vimREG->REQMASKCLR2; } else if (U32_VIM_CHAN0_OFFSET < u32VectorIrqIndex) /* Channel 2-31 */ { vimREG->REQMASKCLR0 = ((U32_REG_CLRMASK << (U32_CHAN_REG0_OFFSET(u32VectorIrqIndex))) & (~vimREG->FIRQPR0)); vimREG->REQMASKCLR1 = ( U32_REG_CLRMASK & (~vimREG->FIRQPR1)); vimREG->REQMASKCLR2 = ( U32_REG_CLRMASK & (~vimREG->FIRQPR2)); vimREG->REQMASKCLR3 = ( U32_REG_CLRMASK & (~vimREG->FIRQPR3)); /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ vimREG->REQMASKCLR3 = vimREG->REQMASKCLR3; vimREG->REQMASKCLR2 = vimREG->REQMASKCLR2; } else /* FIQ is not executed in this context*/ { ErrHdl_vSetErrCodeDummy; /* Reaction Safe Mode */ } _enable_IRQ(); /* Enable IRQ, to allow preemption of IRQ routine */ (*pf_irqFunc)(); /* Execute interrupt routine */ _disable_IRQ(); /* Disable IRQ, to protect the remainder of the dispatcher from preemption */ /* Restore VIM REQENASET[0,1,2,3] Registers */ vimREG->REQMASKSET0 = u32BckupREQMASKSET0; vimREG->REQMASKSET1 = u32BckupREQMASKSET1; vimREG->REQMASKSET2 = u32BckupREQMASKSET2; vimREG->REQMASKSET3 = u32BckupREQMASKSET3; } else /*index is not valid */ { ErrHdl_vSetErrCodeDummy; /* Reaction Safe Mode */ } }
and the function pointer itself points to..
/* SourceId : DMA_SourceId_019 */ /* DesignId : DMA_DesignId_016 */ /* Requirements: HL_SR181, HL_SR182 */ void dmaBTCAInterrupt(void) { uint32 offset = dmaREG->BTCAOFFSET; /* USER CODE BEGIN (6) */ /* USER CODE END */ if (offset != 0U) { dmaGroupANotification(BTC, offset - 1U); } /* USER CODE BEGIN (7) */ /* USER CODE END */ }
Kindly let me know if you need any other information on this.
Thank you and have a lovely day..