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TM4C1230H6PM: Can not generate HEXFILE of fix line length

Divyesh Tilva
Prodigy 40 points
Part Number: TM4C1230H6PM

I am using above mentioned MCU with CCS Version: 10.3.1.00003 .

I have created  two project one is bootloader and second is actual application.

In bootloader i have used ARM compiler having version TI v20.2.4 LTS and have generated hexfile using ARM hexfile utility with option --memwidth=8 --romwidth=32 --diag_wrap=off --intel.Hexfile is generated but hex record have size of 32 bytes(data only).Also there is some lines which has length less than 32 bytes but i want all lines of HEXFILE having same length either 16 or 32 bytes.

Also in second project i have used GNU compiler v7.2.1(Linaro) and using GNU objcopy Utility i have generated HEXFILE which has hexrecord of 16 bytes and some lines have less than 16 byte data.

My purpose is that i have to generate hexfile with fix length in both cases either 16 or 32 bytes both remain same in both projects.

Also i have try below command but not getting expected output instead of getting same as above described.

C:\ti\ccs1031\ccs\tools\compiler\gcc-arm-none-eabi-7-2017-q4-major-win32\bin\arm-none-eabi-objcopy.exe -O srec --srec-len 0x10 "iocard_v3.elf" "iocard_v3.srec";
C:\ti\ccs1031\ccs\tools\compiler\gcc-arm-none-eabi-7-2017-q4-major-win32\bin\arm-none-eabi-objcopy.exe -I srec -O ihex iocard_v3.srec iocard_v3.hex

Kindly Help to resole this.

  • +1
    TI__Guru 72500 points

    I cannot comment on the GNU tools, but for the TI tools the reason that some lines have less than 32 bytes is that the sections in the ELF file do not all have a multiple of 32 bytes. Each section will start a new line in the Intel Hex file generated by ARMHEX.

    You can force padding in each section by adding the "palign" command to the SECTIONS directive of the linker command file. Here is the documentation on the "palign" command from the ARM Assembly Language Tools User's Guide.

    Here is an example of the sections part of a modified linker command file:

    /* Section allocation in memory */

SECTIONS
{
    .intvecs:  palign(32) > APP_BASE
    .text   :  palign(32) > FLASH
    .const  :  palign(32) > FLASH
    .cinit  :  palign(32) > FLASH
    .pinit  :  palign(32) > FLASH
    .init_array : palign(32) > FLASH

    .vtable :   > RAM_BASE
    .data   :   > SRAM
    .bss    :   > SRAM
    .sysmem :   > SRAM
    .stack  :   > SRAM
}