Dear TI Experts,
Good day.
Part number: TMS570LC4357. I follow ti's guide on sharing exception vectors here: www.ti.com/.../spna236.pdf but it seems when the application code attempts to use the SWI interrupt, instead of taking the branch in the RAM table it instead interprets the address in the RAM table as an instruction, seemingly skipping the branch instruction entirely
the RAM table in question. it is supposed to load the .word vPortSWI into the program counter but instead tries to run the address of vPortSWI as an instruction, generating a prefetch abort.
Please see attached:
sn_customerservice_case_32bf49111b6cf4dcad92ba63164bcb74_attachments.zip
Thank you in advance for the usual help.
Regards,
Jonard Rico
