Other Parts Discussed in Thread: TEST
- Is JTAG RTCK required for target connection?
- What are the dfifference between JTAG and ETM?
- Why should the nTRST signal be pulled LOW?
- The JTAG connection is lost after the program is loaded to flash.
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Is JTAG RTCK required for target connection?
RTCK is not a standard JTAG signal. The asynchronous TAP controller does not require local synchronization, so the RTCK is not a MSUT.
But, occasionally a target device requires the JTAG interface to be externally synchronized to a clock within the device due to it being slow, non-continuous, or variable. The adaptive clocking feature uses the RTCK to address this requirement. When adaptive clocking is enabled, the debug unit issues a TCK signal and waits for the RTCK signal to return before sampling TDO.
If you emulator supports adaptive clock feature, and you are planning to use this feature, you need RTCK from the target device.
What are the differences between JTAG and ETM?
JTAG: The functionality usually offered by JTAG is Debug Access and Boundary Scan: 1. Debug Access is used by debugger tools (for example XDS110, XDS2x) to access the internals of a chip making its resources and functionality available and modifiable, e.g. registers, memories and the system state. 2. Boundary Scan is used by hardware test tools to test the physical connection of a device, e.g. on a PCB. This is usually not the task of a debugger tool.
ETM: The Embedded Trace Macrocell (ETM) interface enables you to connect an external ETM unit (for example XDS560V2 Pro) to the processor for real-time code tracing of the core. JTAG signals are also required for ETM trace.
Why should the nTRST signal be pulled LOW?
nTRST is JTAG “Test Reset”. It is low active. The nTRST is used for an asynchronous reset of the state machine of the JTAG Test Access Port (TAP). The debugger drives it by a push-pull driver. It resets the TAP by a certain JTAG sequence. The target device requires that the nTRST is first held low for a few TCK cycles and then raised after the TCK signal has started running, so the device can detect a rising edge on nTRST.
A pull-down resistor should be added onto nTRST on target side. It ensures the on-chip debug logic is inactive when the debugger is not connected.
From the debugger point of view, nTRST is optional.
The JTAG connection is lost after the program is loaded to flash.
The problem might be caused by the code you have programmed. The code in the flash makes the CPU enter an exception state repeatedly, and the CPU is not able to enter a debug state.
Please try this procedure to let CPU enter a debug state:
5. Please refer to the following link for more information to trouble shoot the JTAG connection issues: