Other Parts Discussed in Thread: TMS570LS3137
Hello TI,
We are using TMS570LS3137 processor. We have done SCI and DMA configurations as given below
SCI:
Multibuffer mode - Enabled
Rx DMA - Enabled.
No.of bytes - 8
DMA:
Ch: 1 to transfer data from ADC 1
Ch: 2 to transfer data from SCI 1
Ch: 3 to transfer data from ADC 2
From the SCI port. we are expecting16 bytes of data from an external unit and we have configured RAM buffer(16 bytes) as DMA destination. We are able to to receive all 16 bytes of data through DMA. As the data from external is asynchronous in nature, we would like to avoid concurrence access of the destination RAM buffer by both DMA and CPU. ie. We want to ensure that there is no DMA write is happening at a particular RAM address, when we read the same. We tried to use DMA current destination pointer to know where the next DMA write is going to happen. However it always shows the same address(address of the RAM buffer[9].
Please let us know what could be the issue here.
Thanks,
Sundaram
