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TM4C123GH6ZRB: tm4c123g microwire falling edge detection

Part Number: TM4C123GH6ZRB

Hi fellows,

is there any possibility to change the Microwire Frame Format in a way so that it uses falling edge detection?

I am working on a project where I use the AD9826. The Microwire format works fine for sending but not for receiving messages.

I verified it on an oscilloscope and the issue is, that for receiving the signal properly I need falling edge detection.

Any suggestions?

Greets Johannes

  • HI,

      

    I am working on a project where I use the AD9826. The Microwire format works fine for sending but not for receiving messages.

     I'm not familiar with AD9826. Doesn't it output data on the falling edge? MCU will latch the data on the rising edge of clock. 

    MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
    full-duplex and uses a master-slave message passing technique. Each serial transmission begins
    with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
    transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
    slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
    been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
    total frame length anywhere from 13 to 25 bits.
    In this configuration, during idle periods:
    ■ SSInClk is forced Low
    ■ SSInFss is forced High
    ■ The transmit data line SSInTx is tristated
    A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSInFss
    causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
    shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the
    SSInTx pin. SSInFss remains Low for the duration of the frame transmission. The SSInRx pin
    remains tristated during this transmission.
    The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
    SSInClk. After the last bit is latched by the slave device, the control byte is decoded during a one
    clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto
    the SSInRx line on the falling edge of SSInClk. The SSI in turn latches each bit on the rising edge
    of SSInClk. At the end of the frame, for single transfers, the SSInFss signal is pulled High one
    clock period after the last bit has been latched in the receive serial shifter, causing the data to be
    transferred to the receive FIFO.

    You need to make sure you are meeting the setup time required by MCU which is 17.5ns from RX to rising edge of SSICLK. If you cannot meet this time then you may need to slow down the clock to see if that helps. 

  • I'm also confused with your scope capture. It looks like the SDATA comes out on the rising edge as opposed what is shown in AD9826 datasheet which shows SDATA should come out on falling edge so the master device can sample on the rising edge. You should show your diagram to the AD9826 vendor as this is not a TI product and I have no knowledge about it. 

  • Thanks for looking into detail into this issue. I will get in contact with the vendor. When it works with the TM4C123... I will post my solution here.

  • Hi Charles, the problem was the wrong frame format. I used the Microwire frame format, which did not work. Changing the format to the freescale one did work out.