Hello,
I have a customer designing with TM4C129 and they are using the TM4C as an SSI slave with the master being clocked off its own crystal/ oscillator. Are there any concerns with slight frequency variations due to oscillator or PLL drift/ jitter with clocking the SPI bus at 10 MHz even if the clock ends up being slightly above 10 MHz?
Munan
Hi,
I don't think that will be an issue. Please make sure timing parameters shown in the datasheet are met for slave mode.
Note: SYSCLK or ALTCLK is used as the source for the SSInClk depending on how the CS field
in the SSI Clock Configuration (SSICC) register is configured. For master legacy mode,
the SYSCLK or ALTCLK must be at least two times faster than the SSInClk, with the
restriction that SSInClk cannot be faster than 60 MHz. For slave mode, SYSCLK or ALTCLK
must be at least 12 times faster than the SSInClk. In slave legacy mode, the maximum
frequency of SSInClk is 10 MHz.
