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TM4C1294NCPDT: Why are there two pins for EPI0S0, 1, 2, and 3 on TM4C1294NCPDT?

Part Number: TM4C1294NCPDT

Why are there two pins for EPI0S0, 1, 2, and 3 on TM4C1294NCPDT?

I would like to know how to use it, if there is one.
Or would you like to know which one you can use?
I want to use it to connect my SDRAM.

  • Hi Yoshitsugu-scan,

      It is not just EPI0SO,1,2,3 have multiple pin options, many other modules also have their functional pins available on multiple device pins. This is to allow flexibility. For EPI0S0, it is available on PK0 as well as PH0. It is up to you to configure one of them for EPI0S0 while using the other one as GPIO. 

      There is actually one EPI example configured to interface with SDRAM. You can find in C:\ti\TivaWare_C_Series-2.2.0.295\examples\peripherals\epi\sdram.c