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TM4C123GH6PGE: SSI/SPI frame format with SSI position encoder

Part Number: TM4C123GH6PGE
Other Parts Discussed in Thread: EK-TM4C1294XL

I'm using the TM4C123GXL launchpad to determine if the ARM M4 series microcontrollers will work for my application, which includes an SSI position encoder (iC-MU). The timing spec for the encoder is as follows:

The t_tos spec is 1.5Xt_MAS (which is just the clock period), so it scales with clock speed. The encoder message is 32 bits long, so this means I need to produce a clock signal with the SSI peripheral which has 32 clock periods, and it can't have a gap two clock periods wide after the 16th bit or it will time out.

After doing some tinkering with this launchpad it seems the SSI peripheral on this Tiva C series can't be configured this way, because it has to pause between 16 bit writes to the TX FIFO (image and explanation are from this post):

In the case of a single word transmission, after all bits of the data word have been transferred, the
SSInFss line is returned to its idle High state one SSInClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSInFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned
to its idle state one SSInClk period after the last bit has been captured.

So my question is this: Am I correct in thinking that there is no way to use this MCU to talk to this encoder (using its SSI interface) without it timing out in the middle of a message? Or is there a way to produce a SPI clock signal without any gaps between TX FIFO entries like you can with C2000 devices?

Thank you!