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LP-AM243: GPIO interrupt config

Part Number: LP-AM243
Other Parts Discussed in Thread: SYSCONFIG

I am using the standard board  LP-AM243 for an application 

gpio_input_interrupt_am243x-lp_r5fss0-0_nortos_ti_arm-clang 

The interrupt mapped to the push button 

 intrNum         = Board_getGpioButtonIntrNum();

#define BOARD_BUTTON_GPIO_INTR_NUM (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8)
#define BOARD_BUTTON_GPIO_SWITCH_NUM (5)

How is this interrupt number mapped to this button 

I have to map the following pins to the interrupts 

GPIO1_0   (J4)      - J3

GPIO1_1   (J4)      -J4

GPIO1_2    (J4)     -G1

GPIO1_32  (J8)     -P2

GPIO1_33  (J8)     -T4

  • Hi Dinesh,

    GPIO interrupts are routed through the GPIO interrupt routers before arriving at destination interrupt controllers in the R5F and ICSSG sub-systems.

    For details on GPIO interrupts, see the AM64x/AM243x TRM (spruim2c.pdf) 12.1.2.4.3 GPIO Interrupt and Event Generation.

    For details on GPIO interrupt connections, please refer to these TRM sections:

    • 12.1.2.3.2 GPIO Integration in MAIN Domain
    • 12.1.2.4.4 GPIO Interrupt Connectivity
    • 9.3.2.2 GPIOMUX_INTRTR0 Integration
    • 9.3.3.1 GPIOMUX_INTRTR0 Registers
    • 9.4.1.2 R5FSS0_CORE0 Interrupt Map

    The example gpio_input_interrupt_am243x-lp_r5fss0-0_nortos_ti_arm-clang uses GPIO1_54 (B9).

    GPIO1_54 is in GPIO Bank 2, so this GPIO can generate an interrupt on GPIO Bank interrupt 2.

    GPIOMUX_INTRTR0 is configured in board.c:Sciclient_gpioIrqSet():

    • GPIO Bank interrupt 2 is connected to GPIOMUX_INTRTR0 Input #182 (see TRM Figure 12-57. GPIO Integration)
    • GPIO Bank interrupt 2 is routed through GPIOMUX_INTRTR0 Output #8, i.e. GPIOMUX_INTRTR0_MUXCNTL_8 is set to 182 (0xB6)
    • GPIOMUX_INTRTR0 Output #8 is connected to R5F VIM interrupt #40 (see TRM Table 9-80. R5FSS0_CORE0 Interrupt Map).

    Sciclient_gpioIrqSet() can be used to route any GPIO1 Bank interrupt through GPIOMUX_INTRTR0, but note the function is hard-coded for GPIO1 and would need to be updated to handle GPIO0.

    The remainder of the interrupt configuration occurs in gpio_input_interrupt_main():

    • The GPIO bank interrupt is enabled in gpio_input_interrupt_main() by the call to GPIO_bankIntrEnable(gGpioBaseAddr, bankNum)
    • The R5F interrupt #40 is configured and enabled by the call to HwiP_construct().

    Other GPIO modules and pins can be selected in Sysconfig by modifying the GPIO parameters in example.syscfg. For example, to change the example code to use GPIO1_0, simply update the GPIO pin from B9 to J3 and recompile the CCS project. Sysconfig will update the pinmux and driver configurations in these files:

    • ti_drivers_config.h : "GPIO_PUSH_BUTTON" pin number updated
    • ti_pinmux_config.c  : gPinMuxMainDomainCfg[] updated to configure J3 for GPIO1_0

    Adding GPIO interrupts in a single GPIO Bank would require:

    • Adding new GPIO pins to Sysconfig
    • Adding calls to functions like GPIO_setDirMode() and GPIO_setDirMode() for new pins
    • Updating GPIO bank ISR function GPIO_bankIsrFxn() to process interrupts more than a single GPIO pin (e.g. perhaps change the ISR args to a pin mask instead of a pin number).

    Adding GPIO interrupts from more than a single GPIO Bank would require:

    • Adding new GPIO pins to Sysconfig
    • Adding calls to functions like GPIO_setDirMode() and GPIO_setDirMode() for new pins
    • Updating Sciclient_gpioIrqSet() to take the GPIO1 bank number and R5F VIM input interrupt numbers as a parameters
    • Adding a call to Sciclient_gpioIrqSet() for the new interrupt route
    • Adding new R5F VIM interrupt configuration via call to HwiP_construct().

    Please let me know if anything needs clarification, or more information is required.

    Regards,
    Frank

  • What are the interrupt nos for the following Pins?

    GPIO1_0   (J4)      - J3

    GPIO1_1   (J4)      -J4

    GPIO1_2    (J4)     -G1

    GPIO1_32  (J8)     -P2

    GPIO1_33  (J8)     -T4

  • Thanks for giving me the description. Can you please give me the nos ...

  • Hi Dinesh,

    The GPIO interrupts don't have a fixed mapping to the R5SS VIM INTC's since they go through the GPIO Interrupt Router.

    In the GPIO interrupt example, GPIO1_43 is used. GPIO1_43 maps to GPIO1 Bank interrupt 2 (floor(43/16)=2).

    The interrupt configuration is as follows:

    • BANK interrupt 2 → MAIN_GPIO_INTRTR_IN_182
    • MAIN_GPIO_INTRTR_IN_182  →  MAIN_GPIOMUX_INTROUTER0_OUTP_[8] (Figure 9-19. GPIOMUX_INTRTR0 Integration, this INTR Router Output is allocated to R5F0_0 in Sciclient lib)
    • MAIN_GPIOMUX_INTROUTER0_OUTP_[8] → R5FSS0_CORE0/1_INTR_IN_[40]

    This means GPIO1 Bank interrupt 2 is routed to VIM interrupt #40.

    GPIO1_32 & 33 use the same GPIO1 Bank Interrupt 2 ((floor(32/16)=2 & floor(33/16)=2). Hence these GPIO pins can use the same R5FSS 0 VIM interrupt #40.

    GPIO1_0, 1 & 2  use GPIO1 Bank Interrupt 0. The GPIO1 Bank interrupt 0 can be routed to R5FSS 0 VIM interupt #41 as follows:

    • BANK interrupt 0 →  MAIN_GPIO_INTRTR_IN_180
    • MAIN_GPIO_INTRTR_IN_180 →  MAIN_GPIOMUX_INTROUTER0_OUTP_[9] (Figure 9-19. GPIOMUX_INTRTR0 Integration, this INTR Router Output is allocated to R5F0_0 in the Sciclient lib)
    • MAIN_GPIOMUX_INTROUTER0_OUTP_[9] → R5FSS0_CORE0/1_INTR_IN_[41]

    Regards,
    Frank