When setting up the PLL and clocking, I expected to get 80 MHz. My test loop has 7 instructions in it and it produces 5.7MHz square wave
Assuming 1 clock per instruction (that's an assumption), the system clock is 40 MHz.
If each instruction takes 2 clocks, then everything is working correctly.
I use the following call from the SDK
SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_25MHZ |