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Initializing RAM and ECC

Brian Fortman
Expert 7650 points

I'm a bit confused by Section 3 of the ECC application note SPNA126.  In 3.1 it says "To avoid these false double bit errors, you must initialize RAM and its ECC space before enabling the ECC."  But, in 3.2 and 3.3, we are instructed to Enable ECC then initialize memory (either by software or auto-initialization). 

Can you clear this up for me?

  • 0
    TI__Intellectual 2285 points

    Brian,

    The 3.1 section is supoposed to mean "To avoid these false double bit errors, the user must initialize RAM and its ECC space before using the ECC."

    I'm in the process of updating this app note with few more items.

    Regards,

    Pratip

  • 0 in reply to Pratip Kumar
    TI__Mastermind 30845 points

    Brian,

    In trying to cover the different ECC mechanisms in TMS570, TMS470M, etc, the ECC app note became a bit unclear. We will work on improving the readability of this document.

    Here's some more information to help clarify:

    The ECC mechanism embedded in the R4 (TMS570) is always on. And with that I mean

    - writes to RAM locations will cause RAM ECC bits to be updated.

    When we talk about enabling or disabling RAM ECC, it's scope is actually limited to enabling or disabling error generation and reporting of ECC errors. So if ECC is "disabled" no ECC errors will be reported.

     

    RAM initialization can be done independent of the above being enabled or disabled. The key point to note here is, if ECC is enabled but not initialized, then reads from uninitialized RAM regions will invariably cause ECC errors (double bit errors very likely).

    On a related note, when RAM and RAM ECC is initialized, RAM should read all 0's (obviously) and the RAM ECC bits should read 0x0C through the whole RAM ECC region.

    Hope this helps.

    Regards,
    Abhishek

  • 0 in reply to A Arora
    Prodigy 95 points

    Hello,

    Greate, that explains some of the questions I had.

    Now ... How can I test if the RAM ECC check is working or not? The document  (SPNA126, page 18) provides instuctions on how to introduce an Error into RAM ECC, looking at step 4.. How can I disable the ECC generation logic ?

    Thanks.

    Tareq 

  • 0 in reply to Tareq Alqaisi
    TI__Intellectual 2285 points

    Tareq,

    What is your target device ? Is it Cortex M3 or R4 ?

     

    Step 1

    Initialize RAM                                               

    Follow  section 3.1

    Step 2

    Enable SECDED (ECC logic)                                                 

    This will switch on the ECC generation logic.

    Follow section 3.3.1 for Cortex M3 or ARM7

    Follow section 3.3.2 for Cortex R4

    Step 3

    Write data to a specific RAM location       

    This will generate and load the corresponding ECC check bits.

    Step 4

    Disable SECDED (ECC logic)                                                                                                    

    This will switch off the ECC generation logic so as to enable the user to corrupt data

    Follow section 3.3.3 for Cortex M3 or ARM7

    Follow section 3.3.4 for Cortex R4

    Step 5

    Wait until ECC disabled                              

    Although this step is not mandatory it is to make sure that it flushes the buffers.

    Step 6

    Change only the data in that specific RAM location.

    Flip one/two bit, this will corrupt only the data part.

     

    Step 7

    Enable ECC error interrupt

    This will enable the user to handle the error in the exception routine.

    Step 8

    Enable SECDED (ECC logic)

    This will switch ON the ECC generation logic again and create a scenario to check ECC.

     

    Step 9

    Read the corrupted data.

    The logic will perform an ECC check when the user reads the same data.

     

    Step 10

    Check for single/multiple bit error event

    The ECC logic should generate a bit error.

     

     

     

    3.3.1 Instructions to enable ECC for M3 and ARM7 based CPUs

     

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4 = 0xA; /* enable SECDED */

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4;        /* wait for write to complete */

     

     

    3.3.2 Instructions to enable ECC for R4 based CPUs

     

    In case of controllers with R4 CPU, the ECC generation logic is within the CPU and this needs to be enabled. The ECC in the RAM wrapper should also be enabled before enabling the ECC in R4; this would keep the status registers in the RAM wrapper updated.

     

    a. Enable RAM wrapper ECC:

     

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4 = 0xA; /* enable SECDED*/

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4;         /* wait for write to complete */

     

    b. Enable R4 CPU ECC:

    _ENABLE_ECC_R4_RAM

     

     

           MRC p15,#0,r1,c9,c12,#0    ; Reading secondary Aux secondary Reg.

           ORR r1, r1, #0x00000010   

           DMB

           MCR p15,#0,r1,c9,c12,#0    ; Enable export of the events in PMNC

           ISB                         ; To ensure the write before proceeding

     

     

           MRC p15, #0, r1, c1, c0, #1      

           ORR r1, r1, #0x1 <<26         ; B0TCM ECC Check Enable

           ORR r1, r1, #0x1 <<27         ; B1TCM ECC Check Enable

           DMB

           MCR p15, #0, r1, c1, c0, #1

           ISB                        ; To ensure the write before proceeding

     

           MOV PC, lr   

     

     

     

     

     

    3.3.3 Instructions to disable ECC for M3 and ARM7 based CPUs

     

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4 = 0x5;/* disable ECC */

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4;      /* wait for write to complete */

     

     

    3.3.4 Instructions to disable ECC for R4 based CPUs

     

    In case of controllers with R4 CPU, the ECC within the CPU needs to be disabled. Following this the ECC in the RAM wrapper should be disabled.

     

     

    a. Disable R4 CPU ECC

    _DISABLE_ECC_R4_RAM

          

     

    MRC p15, #0, r1, c1, c0, #1      

           MVN R0,#0x1 <<26                  ; B0TCM ECC check disable

    AND R1 ,R1, R0

           MVN R0,#0x1 <<27                  ; B1TCM ECC check disable

    AND R1 ,R1, R0

           DMB

           MCR p15, #0, r1, c1, c0, #1

           ISB                               ; To ensure the write before proceeding

     

           MRC p15,#0,r1,c9,c12,#0                                  

           MVN R0,#0x00000010                ; Disable export of the events in PMNC

    AND R1 ,R1, R0

     

           DMB

           MCR p15,#0,r1,c9,c12,#0 

           ISB                               ; To ensure the write before proceeding

          

           MOV PC, lr                        

     

     

     

     

    b. Disable RAM wrapper ECC

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4 = 0x5; /* disable ECC */

    ECC_Ptr->RAMCTRL_UN.RAMCTRL_ST.ECC_ENABLE_B4;       /* wait for write to complete */

     

     

     

    Best Regards,

    Pratip 

     

  • 0 in reply to Pratip Kumar
    Prodigy 95 points

    Hello,

    Thanks for your replay.

    Since ECC is always Generated, when I disable SECDED (ECC logic)  as in the step 4 and then do step 5... this will cause the ECC genreation logic to generate a neww ECC that matches the new data.. I tried this method and it doesn't work. Maybe I need to flip a bit the ECC RAM not the Data???

    Thanks

  • 0 in reply to Tareq Alqaisi
    Prodigy 150 points

    Did you get an answer to this question?  I'm wondering the same thing... how do you induce an error when the ECC is always calculated and stored on the R4 architecture?

  • 0 in reply to Lucas Wendling
    Prodigy 95 points

    No, I didn't get any new info, I got an Email saying that I have to disable the ECC in R4 core. However, the code provided doesn't disable the ECC Generation???  We Need some clear and tested instructions.

  • 0 in reply to Tareq Alqaisi
    TI__Mastermind 30845 points

    Tareq,

    The only way to induce errors is into the RAM ECC bits (at address 0x0840 0000). In order to be able to write into that section, you have to set the ECC WR EN bit in the RAMCTRL register to 1.

    As Pratip mentioned in another post, we will make a piece of example code available this week.

    Regards,

    Abhishek