TMS570LC4357: Mechanism To generate ESM Interrupts

Shivam Kakad

Hi Team,

For our application on TMS570LC4357 Controller, we are installing the different handlers for the interrupts which are supported by the VIM module and trying to test them, by injecting the corresponding interrupts. We are successfully able to generate the DMA, GPIO, RTI and other required peripherals, However getting challenges in creating the same for ESM. AS We see, the VIM supports ESM High as well as ESM Low interrupts. We wanted to understand the method with which we can generate the ESM interrupts and handle them as per its cause.

Thus, request team to assist us in getting the list of steps required to generate the ESM interrupt(for group 1 as well as group 2 ).

Regards,
Shivam Kakad

over 4 years ago

0 Frank Livingston over 4 years ago

TI__Mastermind 30108 points

Hi, our expert is out of office until 4/7. Please expect a delayed response.

Also, please see this FAQ: software-dl.ti.com/.../index.html

0 Srihari Manthri over 4 years ago in reply to Frank Livingston

Intellectual 280 points

Hi,

Any update on this issue ? Request your response on the question,

0 QJ Wang over 4 years ago in reply to Srihari Manthri

TI__Guru**** 200246 points

Hi Srihari,

The ESM module collects and reports the various error conditions. Error response is then generated based on the category of the error. Possible error responses include a low priority interrupt, high priority interrupt, and an external pin action.

For ESM group1, the interrupt priority is configurable, for example ESM 1:17:

If it is mapped to low level, any MibSPI1 parity error will be handled by sl_esm_low_intr_handler() (SDL API).

The ESM LOW interrupt can be configured to either IRQ or FIQ:

You can generate the interrupt by injecting a parity error to MibSPI1 RAM.

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LC4357: Mechanism To generate ESM Interrupts