LAUNCHXL2-570LC43: TMS570LC4357

Jayant Singh

I am keeping the COS bit of RTIGCTRL clear, right at the init, but I don't see the effect. The timer continues running while waiting at a breakpoint. I don't have an external clock. The value of NTUSEL is 0h.

over 1 year ago

+1 QJ Wang over 1 year ago

TI__Guru**** 186196 points

Hi Jayant,

For TMS570LC43x, there is an on-chip CTI (Cross Trigger Interface) module that is programmable to route the debug acknowledge signal (DBGACK is asserted when halted) from the CPU to the rest of the devices. The CTI must be enabled first before the rest of the system such as RTI can see the DBGACK being asserted and in consequence stop the counter during debug state.

We updated GEL file to enable/disable CTI. In CCS, you can use "CCS-->Scripts-->Configure Cross Triggering" to enable CTI.

0 Jayant Singh over 1 year ago in reply to QJ Wang

Prodigy 81 points

How can we configure CTI in IAR?

0 Jayant Singh over 1 year ago in reply to Jayant Singh

Prodigy 81 points

I have figured it out. In IAR point the attached macro file Option->Debug->macro

CTI_Configuration.mac.txt

// -----------------------------------------------------------------------
// This file contains the CoreSight Debugger CTI Enable/Disable for TMS570LC4357.
//
//
// $Revision :$
//
//-------------------------------------------------------------------------

//----------------------------------------------------------------------------
// Function - Enable_CTI1                                                     
     
Enable_CTI1( ) 
{
    
    __message	"NOTES:\n\tEnable CTI1\n";

// Unlock writes to CTI
	__writeMemory32(   0xC5ACCE55,0xFFA07FB0,"Memory"    );

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x00000001,0xffa07000,"Memory"    );

/* Map CTITRIGIN0=CortexR5-0 DBGTRIGGER to Channel 0*/
	__writeMemory32(   0x00000001,0xffa07020,"Memory"    );

/* Map CTITRIGIN7=CortexR5-0 DBGTRIGGER to Channel 0-3 */
/* DBGTRIGGER from Cortex-R5-0 is mapped to both CTITRIIN0 and CTITRIIN7 */
	__writeMemory32(   0x00000001,0xffa0703c,"Memory"    );

/* Map CTITRIGOUT0=CortexR5-0 EDBGRQ to Channel 3*/
	__writeMemory32(   0x00000000,0xffa070a0,"Memory"    );

/* Map CTITRIGOUT7=CortexR5-0 DBRESTARTED to Channel 1*/
	__writeMemory32(   0x00000000,0xffa070bc,"Memory"    );

/* Enable all 4 channel interfaces */
	__writeMemory32(   0x00000003,0xffa07140,"Memory"    );

} /* Enable_CTI1 */
/*----------------------------------------------------------------------------*/
/* Function - Enable_CTI2                                                     */
/*                                                                            */
Enable_CTI2() {
    
    __message	"NOTES:\n\tEnable CTI2\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa08fb0,"Memory"    );

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x00000001,0xffa08000,"Memory"    );

/* Map CTITRIGIN0=CortexR5-1 DBGTRIGGER to Channel 0*/
	__writeMemory32(   0x00000000,0xffa08020,"Memory"    );

/* Map CTITRIGIN7=CortexR5-1 DBGTRIGGER to Channel 7*/
/* DBGTRIGGER from Cortex-R5-1 is mapped to both CTITRIIN0 and CTITRIIN7 */
	__writeMemory32(   0x00000000,0xffa0803c,"Memory"    );

/* Map CTITRIGOUT0=CortexR5-1 EDBGRQ to Channel 3*/
	__writeMemory32(   0x00000001,0xffa080a0,"Memory"    );

/* Map CTITRIGOUT7=CortexR5-1 DBRESTARTED to Channel 1*/
	__writeMemory32(   0x00000001,0xffa080bc,"Memory"    );

/* Enable all 4 channel interfaces */
	__writeMemory32(   0x00000003,0xffa08140,"Memory"    );

} /* Enable_CTI2 */

/*----------------------------------------------------------------------------*/
/* Function - Enable_CTI3                                                     */
/*                                                                            */
Enable_CTI3( ) 
{
    
    __message	"NOTES:\n\tEnable CTI3\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa09fb0,"Memory"    );

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x00000001,0xffa09000,"Memory"    );

/* Note: there are no CTITRIGIN[7:0] mapped to CTI3 */

/* Map CTITRIGOUT0=TPIU TRIGIN to Channel 2 */
/* Possible triggers from Channel 2 could be the ETMR5-0/1 EXTOUT[1:0] */
/* The ETMR5_0 EXTOUT[1:0] are mapped to the CTITRIIN[3:2] of the CTI1 */
/* The ETMR5_1 EXTOUT[1:0] are mapped to the CTITRIIN[3:2] of the CTI2 */
	
	__writeMemory32(   0x00000004,0xffa090a0,"Memory"    );

/* Map CTITRIGOUT1=TPIU FLUSHIN to Channel 2 */
/* Possible triggers from Channel 3 could be the ETMR5-0/1 EXTOUT[1:0] */
/* The ETMR5_0 EXTOUT[1:0] are mapped to the CTITRIIN[3:2] of the CTI1 */
/* The ETMR5_1 EXTOUT[1:0] are mapped to the CTITRIIN[3:2] of the CTI2 */

	__writeMemory32(   0x00000004,0xffa090a4,"Memory"    );

/* Since there are no implemented CTITRIGIN there is no need to enable channel interfaces  */
/* for CTICHOUT gating */

	__writeMemory32(   0x0000000F,0xffa09140,"Memory"    );

} /* Enable_CTI3 */

/*----------------------------------------------------------------------------*/
/* Function - Enable_CTI4                                                     */
/*                                                                            */
Enable_CTI4( ) 
{
    
    __message	"NOTES:\n\tEnable CTI4\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa0afb0,"Memory"    );

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x00000001,0xffa0a000,"Memory"    );

/* Map CTITRIGIN0=DMA_DBGREQ to Channel 3 */
	
	__writeMemory32(   0x00000008,0xffa0a020,"Memory"    );

/* Map CTITRIGIN1=N2HET1_DBGREQ to Channel 3 */
	__writeMemory32(   0x00000008,0xffa0a024,"Memory"    );

/* Map CTITRIGIN2=N2HET2_DBGREQ to Channel 3 */
	__writeMemory32(   0x00000008,0xffa0a028,"Memory"    );

/* Map CTITRIGIN3=HTU1_DBGREQ to Channel 3 */
	__writeMemory32(   0x00000008,0xffa0a02c,"Memory"    );

/* Map CTITRIGIN4=HTU2_DBGREQ to Channel 3 */
	__writeMemory32(   0x00000008,0xffa0a030,"Memory"    );

/* Map CTITRIGIN5=DMA_DBGREQ to Channel 3 */
/* DMA_DBGREQ is mapped to both CTITRIGIN0 and CTITRIGIN5. One is pulse and another is level */
	__writeMemory32(   0x00000008,0xffa0a034,"Memory"    );


/* Map CTITRIGIN6=N2HET1_DBGREQ or HTU1_DBGREQ to Channel 3 */
	__writeMemory32(   0x00000008,0xffa0a038,"Memory"    );


/* Map CTITRIGIN7=N2HET2_DBGREQ or HTU2_DBGREQ to Channel 3 */
	__writeMemory32(   0x00000008,0xffa0a03c,"Memory"    );

 
/* Map CTITRIGOUT0=SYS_MODULE_TRIGGER to Channel 0*/
/* When the CPU is halted, the SUSPEND will come from Channel 0 * /
/* The SUSPEND is the result of the assertion on the DBGTRIGGER from the CPU */
/* SYS_MODULE_TRIGGER is broadcasted to L2FMC, CCMR5, CRCx, and SYS modules */
	__writeMemory32(   0x00000001,0xffa0a0a0,"Memory"    );

/* Map CTITRIGOUT0=USER_PERIPHERAL_TRIGGER1 to Channel 0*/
/* USER_PERIPHERAL_TRIGGER1 is broadcasted to: */
/* DMA, RTIx, AWMx, HTUx, SCIx, LINx, I2Cx, EMAC, EQEP, ECAP, DMM and DCCx modules */
	__writeMemory32(   0x00000001,0xffa0a0a4,"Memory"    );

/* Map CTITRIGOUT0=USER_PERIPHERAL_TRIGGER2 to Channel 0*/
/* USER_PERIPHERAL_TRIGGER2 is broadcasted to DCANx modules */
	
	__writeMemory32(   0x00000001,0xffa0a0a8,"Memory"    );

/* Map CTITRIGOUT0=USER_PERIPHERAL_TRIGGER3 to Channel 0*/
/* USER_PERIPHERAL_TRIGGER3 is broadcasted to ETPWMx modules */
	__writeMemory32(   0x00000001,0xffa0a0ac,"Memory"    );


/* Enable channel interfaces  */

	__writeMemory32(   0x0000000F,0xffa0a140,"Memory"    );

} /* Enable_CTI4 */

Disable__CTI1( ) 
{
    
    __message	"NOTES:\n\tDisable CTI1\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa07fb0,"Memory"    );

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x0000000,0xffa07000,"Memory"    );
} /* Disable_CTI1 */

Disable__CTI2() {
    
    __message	"NOTES:\n\tDisable CTI2\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa08fb0,"Memory"    );
 

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x0000000,0xffa08000,"Memory"    );



} /* Disable_CTI2 */

Disable__CTI3( ) 
{
    
    __message "NOTES:\n\tDisable CTI3\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa09fb0,"Memory"    );


/* enable ECT in CTICONTROL */
	__writeMemory32(   0x0000000,0xffa09000,"Memory"    );


} /* Disable_CTI3 */

Disable__CTI4( ) 
{
    
    __message "NOTES:\n\tDisable CTI4\n";

/* Unlock writes to CTI */
	__writeMemory32(   0xc5acce55,0xffa0afb0,"Memory"    );

/* enable ECT in CTICONTROL */
	__writeMemory32(   0x0000000,0xffa0a000,"Memory"    );



} /* Disable_CTI4 */

execUserSetup( )
{
  __message "execUserSetup\n" ;

  Enable_CTI1();
  Enable_CTI2();
  Enable_CTI3();
  Enable_CTI4();
}

Arm-based microcontrollers

Arm-based microcontrollers forum

LAUNCHXL2-570LC43: TMS570LC4357