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AM2634-Q1: maximum QSPI flash size ?

Sung-IL
Mastermind 28755 points
Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634

Dear Champs,

Could you please let me know what is the maximum size of QSPI memory can be attached to AM2634?

When I checked TRM, 0x6000 0000 ~ 0x6200 0000 region(32MBytes) was mapped for QSPI memory in below. Does this mean over 32MBytes QSPI flash memory can not be attached to AM2634?

Thanks and Best Regards,

SI.

  • +1
    TI__Expert 4220 points

    SI,

    I'm not aware of any flash size limits, but here is some clarification and extra considerations:

    the memory region 0x6000 0000-0x6200 0000 is referring to the SFI memory-mapped region. The QSPI system in AM263x is composed of two blocks, SFI_MM_IF and SPI_CORE. The SFI is intended to ease the communication with serial flash devices by memory-mapping its contents to this space in memory via an SFI translator and allows you to also configure external flash settings via SFI register controls. If you want to take full advantage of this interface then you are essentially limited to the size of the memory mapped space. 

    See section 13.3.4.4.1 QSPI Block Diagram, 13.3.4.4.1.1 SFI Register Control, and 13.3.4.4.1.2 SFI Translator of the TRM for more information

    AM263x TRM: https://www.ti.com/lit/ug/spruj17/spruj17.pdf?ts=1656086781553&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FAM2634%253FkeyMatch%253D%2526tisearch%253Dsearch-everything%2526usecase%253Dpartmatches

    However, using this interface block is optional. The size will not be limited to the size of L2_MAIN if you choose not to use it and instead just carry out all your communication via the generic SPI_CORE block, which carries out the standard SPI communication via the SPI interface itself.

    Keep in mind that although you won't be limited by the size of memory-mapped space if carrying out generic SPI communication, AM263x will only support up to 4-byte addressing communication. So this would be in fact the true limiting factor in this case when talking about flash size limit as any address requiring over 32 bits to reach will be virtually inaccessible.

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 28755 points

    Hi Daniel,

    Is there any difference in read/write time between SFI_MM_IF and SPI_CORE?

    Is the only difference in SPI_CORE 'SPI flash command' to indicate flash memory address?

    Thanks and Best Regards,

    SI.

  • +1 in reply to Sung-IL
    TI__Expert 4220 points

    Hi SI,

    read/write times should be the same between SFI and SPI, since SFI still uses the SPI protocol to communicate with flash devices, timings will be the same. It is only a simplified interface for user convenience.

    The only difference is that if using SPI_CORE block then the user will be responsible for setting up communication frames to send to the device by using  the corresponding data registers. Software must load the command into the SPI data transfer register with additional configuration fields, perform the byte transfer, then place the data to be sent (or configure for receive) along with additional configuration fields, and perform that transfer; user will be responsible for this rather than SFI simplifying the operation.

    Best,

    Daniel