TMS570LS0914: workaround with ADC DMA

Thorben Kamp said:

A) What would you recommend?

My recommendation is:

DMA Element Count = G2_Blocks = Fifo Size

Thorben Kamp said:

B) Btw, where are the results stored if we use a fifo size greater than 8? 16 Was Halcogen's default value, althouh there are only 8 buffer register?

If the converted data in FIFO (buffer 0 ~ buffer 7) have been copied to SRAM, the new conversion data will be written to FIFO starting at FIFO[0]. If data has not been read out from FIFO, the new conversion data will be written to FIFO[16:8].

If DMA_EN and BLK_XFER are enabled, the data should be read out before the next conversion starts.

Thorben Kamp said:

c) What does no valid data mean for ADC?

There is a hardware mechanism to protect the application from reading the invalid data in the FIFO. Once all available conversion results have been read out of the FIFO, a  subsequent read from the FIFO causes the mechanism to indicate that the FIFO is empty by setting the EMPTY field.

Thorben Kamp said:

d) When does the block transfer trigger the DMA request? If we set G2_BLK_XFER  to2, will a request be generated after the second valid or after the seconf measurement?

G2_BLK_XFER can be programmed to 0x0 or 0x1. 2 is not valid. 

G2_BLK_XFER = 1 --> ADC module generates a DMA request when the ADC has written G2_BLOCKS number of buffers into the Group2 memory.

Thank you, we will try it. In d) we meant "If we set G2_BLOCKS to2, .[..]", but i guess its answered anyway.

we have noticed that the value of  G2_BLOCKS is changing during runtime. in the adc_init it is set to 2.
while our applcation runs,we send out the value over CAN and the value is flucuating between 1-8.

Do you have an idea, why it is changing?

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Edit: we habe observed, if we set GxINTCR = Fifo_size , G2_BLOCKS is set to Fifo_size as well. Now Fifo size is set to 2.