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RM48L952: Parallel Bus

Part Number: RM48L952

Hi,

I want to interface my 16-bit data bus SRAM with RM48L952 with Parallel interface.

Also for communication , I am using EtherCAT which also needs 16-bit  EMIF interface with RM48L952

Can you suggest with RM48 part has 2 parallel bus to support both SRAM and EtherCAT.

Thanks, Reshma

  • Hi Reshma,

    I don't understand how you want use EMIF for EtherCAT communication.

    The purpose of EMIF is to interface external memories(SDRAM, SRAM and NOR Flash) to the CPU.

    In general for EtherCAT communication, EMC/MDIO will be used in controller. And this module uses the Media Independent Interface (MII) and/or Reduced Media Independent Interface (RMII) to physical layer device (PHY).

    I just verified whether EMIF pins are overlapping with MII/RMII pins in RM48 controller and i found there is no overlapping between them in the both 144 and 337 pin Packages. So you can use both the communications at a time(parallelly).

    --

    Thanks,
    Jagadish.

  • Hi Jagadish,

    Thanks for your response.

    We have used RM48L952 EMIF interface with EtherCAT chip(FIDO5200) in Parallel Host bus Configuration.

    FIDO5200 has 16 data lines and 4 address lines, which we connected to EMIF lines on RM48.

    Now we have requirement to use SRAM( 8 data lines and address lines) parallel bus.

    EMIF data lines D0 to D15 data lines connected to FIDO chip and D16 to D31 connected to SRAM.

    EMIF address lines A0 to A3 lines connected to FIDO and A4 to A11 connected to SRAM for independent address configuration.

    So I need to know if SRAM can  be given on left out EMIF lines.

    Also can both devices work parallelly in this configuration. Please confirm

    Please let me know if you have any clarifications.

    Thanks,

    Reshma

  • Hi Reshma,

    Using different address and data lines for both the devices might not solve the problem because when you writing some data into particular address it just affect the all data lines and address lines of EMIF and we cant control to affect only one particular device address lines and data lines.

    Instead of this, to connect multiple devices parallelly to EMIF peripheral you can just use multiple chip selects.

    If you see above memory map of EMIF you can notice that CS2 will be active for address ranges 0x6000 0000 to 0x6400 0000
    similarly CS3 will be active for address ranges 0x6400 0000 to 0x6800 0000
    and CS4 for 0x6800 0000 to 0x6C00 0000

    So you can just connect different CS pins of controller to different devices(one for FIDO5200 and other for SRAM). In this case you no need to differentiate address lines and data lines. You can commonly use same data and address lines, depends on what address ranges you are accessing in application the corresponding CS will get activate and that corresponding devices will fetch the address and data on the lines.

    You can refer below diagram for tentative hardware interconnect

    Note: In above diagram i used BA0 and BA1 lines also for address lines because according to asynchronous EMIF interface depends on memory type(8bit or 16bit) BA lines also acts as address lines. for more details refer "21.2.6.1 Interfacing to Asynchronous Memory" in TRM. 

    Based on your previous information i understood like SRAM is 8bit and FIDO5200 is 16 bit in your application, so that i interconnected like that.
    My suggestion for you is, i didn't refer the datasheets of SRAM and  FIDO5200, so please refer datasheets before finalize the connections.


    --
    Thanks,
    Jagadish.

  • Hi Jagadish,

    Thanks for the details.

    Have understood the connectivity between devices.

    But still I am not sure if I want to read data from FIDO chip and write data into SRAM or vice versa

    Can these both operations occur at same time?

    Please clarify

  • Hi Reshma,

    If we connect CS2 to SRAM then its address range is from 0x6000 0000 to 0x6400 0000 and 
    If we connect CS3 to FIDO then its address range is from 0x6400 0000 to 0x6800 0000.

    So just assume that you assigned a pointer to the starting address of SRAM i.e. 0x6000 0000 in your application and you are trying to write some data like 0xAA on to that pointer, in this situation EMIF will just activate the chip select of SRAM only(i.e.CS2) and it write the LSB of the address(0x6000 0000) i.e. 0x00 in this case on to the Address and BA lines and it writes the data 0xAA on the data lines. So now SRAM will sample both address and data lines, and performs the write operation(Remember in this case FIDO cant sample address and data lines because its chip select is inactive and that is because the address we are accessing is not in FIDO address range), so it is nothing but we are writing 0xAA into the 0x00 address location of SRAM.

    Similarly if i try to write 0xBB in the address of 0x60000001, then it is nothing but writing 0xBB in the 0x01 address location of SRAM.

    Same process will applicable for FIDO as well but address range is different, If i try to write some 0xCC in the address of 0x6400 0000, then only CS3 will get activate in this case as it is CS3 address range, and EMIF module will put least nibble of the address 0x64000000 into the address lines and BA lines and it will also put the 0xCC on to the data lines. After this FIDO will sample the address and data lines(Remember in this case SRAM cant sample address and data lines because its chip select is inactive and that is because the address we are trying to access is not in SRAM address range). So it is nothing but writing 0xCC into the 0x0 address of FIDO.

    Similarly if i try to write 0xDD in the address of 0x64000001, then it is nothing but writing 0xDD in the 0x1 address location of FIDO.

    I hope this clarifies your doubts.

    --

    Thanks,
    Jagadish.

  • Have understood your explanation.

    Will get back to you if further queries.

    Thanks!!