ADC0 works but ADC1 not. I have to change the udma channel from 14 to 24 because i need the channel 14 for diffrent thing.
So i have to use now the adc1 and not the adc0.
When i use the Code with ADC1 the dma Interupt comes immediately after start the dma channels.
And the dma dont transfer the items. And i get a lot of overflows.
My Code:
void ADC0Seq0IntHandler(void) { ADCIntClear(ADC0_BASE, 0); DEBUG_PA2 = GPIO_PIN_2; // ADC Int if ((uDMAChannelModeGet(UDMA_CH14_ADC0_0 | UDMA_PRI_SELECT) == UDMA_MODE_STOP) && (uDMAChannelModeGet(UDMA_CH14_ADC0_0 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)) { DEBUG_PC4 = 0; // Rec MAP_uDMAChannelDisable(UDMA_CH14_ADC0_0); MAP_ADCSequenceDisable(ADC0_BASE, 0); MAP_ADCIntClear(ADC0_BASE, 0); MAP_ADCSequenceDMADisable(ADC0_BASE, 0); MAP_ADCIntDisable(ADC0_BASE, 0); MAP_IntDisable(INT_ADC0SS0); ADCSequenceOverflowClear(ADC0_BASE, 0); ADCSequenceUnderflowClear(ADC0_BASE, 0); } overflow = ADCSequenceOverflow(ADC0_BASE, 0); underflow = ADCSequenceUnderflow(ADC0_BASE, 0); if (overflow) { ADCSequenceOverflowClear(ADC0_BASE, 0); overflowCounter++; } if (underflow) { ADCSequenceUnderflowClear(ADC0_BASE, 0); underflowCounter++; } DEBUG_PA2 = 0; // ADC Int }
void ADC1Seq0IntHandler(void) { ADCIntClear(ADC1_BASE, 0); DEBUG_PA2 = GPIO_PIN_2; // ADC Int if ((uDMAChannelModeGet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT) == UDMA_MODE_STOP) && (uDMAChannelModeGet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT) == UDMA_MODE_STOP)) { DEBUG_PC4 = 0; // Rec MAP_uDMAChannelDisable(UDMA_CH24_ADC1_0); MAP_ADCSequenceDisable(ADC1_BASE, 0); MAP_ADCIntClear(ADC1_BASE, 0); MAP_ADCSequenceDMADisable(ADC1_BASE, 0); MAP_ADCIntDisable(ADC1_BASE, 0); MAP_IntDisable(INT_ADC1SS0); ADCSequenceOverflowClear(ADC1_BASE, 0); ADCSequenceUnderflowClear(ADC1_BASE, 0); } overflow = ADCSequenceOverflow(ADC1_BASE, 0); underflow = ADCSequenceUnderflow(ADC1_BASE, 0); if (overflow) { ADCSequenceOverflowClear(ADC1_BASE, 0); overflowCounter++; } if (underflow) { ADCSequenceUnderflowClear(ADC1_BASE, 0); underflowCounter++; } DEBUG_PA2 = 0; // ADC Int }
void init_uDMA_MIC0() { // adc mic setup MAP_uDMAChannelAttributeDisable(UDMA_CH14_ADC0_0, UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); MAP_uDMAChannelControlSet(UDMA_CH14_ADC0_0 | UDMA_PRI_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4); MAP_uDMAChannelControlSet(UDMA_CH14_ADC0_0 | UDMA_ALT_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4); MAP_uDMAChannelAttributeEnable(UDMA_CH14_ADC0_0, UDMA_ATTR_USEBURST); }
void init_uDMA_MIC1() { // adc mic setup MAP_uDMAChannelAttributeDisable(UDMA_CH24_ADC1_0, UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); MAP_uDMAChannelControlSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4); MAP_uDMAChannelControlSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4); MAP_uDMAChannelAttributeEnable(UDMA_CH24_ADC1_0, UDMA_ATTR_USEBURST); }
void init_ADC0() { MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)); // adc mic setup MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2); ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1); SysCtlDelay(10); MAP_IntDisable(INT_ADC0SS0); MAP_ADCIntDisable(ADC0_BASE, 0); MAP_ADCSequenceDisable(ADC0_BASE, 0); MAP_ADCHardwareOversampleConfigure(ADC0_BASE, ADC_HARDWARE_OVERSAMPLE); MAP_ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_ALWAYS, 0); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH5 | ADC_CTL_IE); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH5 | ADC_CTL_IE); }
void init_ADC1() { MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1); while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC1)); // adc mic setup MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2); ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1); SysCtlDelay(10); MAP_IntDisable(INT_ADC1SS0); MAP_ADCIntDisable(ADC1_BASE, 0); MAP_ADCSequenceDisable(ADC1_BASE, 0); MAP_ADCHardwareOversampleConfigure(ADC1_BASE, ADC_HARDWARE_OVERSAMPLE); MAP_ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_ALWAYS, 0); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH5 | ADC_CTL_IE); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH5); MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_CH5 | ADC_CTL_IE); }
// // ADC0 // MAP_uDMAChannelTransferSet(UDMA_CH14_ADC0_0 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, (void *)(ADC0_BASE + ADC_O_SSFIFO0), &ADCBufferForFft, FFT_SIZE); MAP_uDMAChannelTransferSet(UDMA_CH14_ADC0_0 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, (void *)(ADC0_BASE + ADC_O_SSFIFO0), &ADCBufferForFft[FFT_SIZE], FFT_SIZE); MAP_uDMAChannelEnable(UDMA_CH14_ADC0_0); MAP_ADCSequenceEnable(ADC0_BASE, 0); MAP_ADCIntClear(ADC0_BASE, 0); MAP_ADCSequenceOverflowClear(ADC0_BASE, 0); MAP_ADCSequenceUnderflowClear(ADC0_BASE, 0); MAP_ADCSequenceDMAEnable(ADC0_BASE, 0); MAP_ADCIntEnable(ADC0_BASE, 0); MAP_IntEnable(INT_ADC0SS0);
// // ADC1 // MAP_uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, (void *)(ADC1_BASE + ADC_O_SSFIFO0), &ADCBufferForFft, FFT_SIZE); MAP_uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, (void *)(ADC1_BASE + ADC_O_SSFIFO0), &ADCBufferForFft[FFT_SIZE], FFT_SIZE); MAP_uDMAChannelEnable(UDMA_CH24_ADC1_0); MAP_ADCSequenceEnable(ADC1_BASE, 0); MAP_ADCIntClear(ADC1_BASE, 0); MAP_ADCSequenceOverflowClear(ADC1_BASE, 0); MAP_ADCSequenceUnderflowClear(ADC1_BASE, 0); MAP_ADCSequenceDMAEnable(ADC1_BASE, 0); MAP_ADCIntEnable(ADC1_BASE, 0); MAP_IntEnable(INT_ADC1SS0);