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[FAQ] TMS570LC4357: Questions regarding FEE (EEPROM) usage on Hercules Microcontrollers

Part Number: TMS570LC4357
  1. What are the difference between EEPROM and Flash Emulated EEPROM (FEE)?
  2. Is emulated EEPROM protected by ECC, and how to enable FEE ECC check?
  3. How can I enable the single and double bit Error Corrections?
  4. Is Checksum used for FEE block protection, and what is the Checksum algorithm used in FEE driver?
  5. What is the weakness of Fletcher-16 checksum?
  6. Can we call all the FEE APIs in USER mode?
  7. Can I call TI_Fee_Init() API more than one time?
  8. What happens if there is a RESET during flash is been erasing?
  9. What happens if there is a RESET during writing data?
  10. Can I call TI_Fee_Init() API more than one time?
  11. Can I run FEE operation in interrupt ISR
  • 1. What are the difference between EEPROM and Flash Emulated EEPROM (FEE)?

    The EEPROM is connected to the host microcontroller via a serial interface. The I2C and SPI are quite popular due to the minimal number of pins. The most of EEPROM allows byte-by-byte program or erase operations. Compared to EEPROM, FEE has higher density. Every FEE location reads 0xFFFF after erased. Through programming, the cell can be changed to logical 0. Any word can be overwritten to change a bit from logical 1 to 0; but not the other way.

    The major difference between EEPROM and FEE is the time for write and erase. A typical FEE write time is 40µs/144-bit word; whereas, EEPROM typically requires 5 to 10ms.

    2. Is emulated EEPROM protected by ECC, and how to enable FEE ECC check?

    Yes, access to the FEE flash bank (bank 7) is protected by dedicated SECDED logic inside the digital interface to the flash banks. The ECC protection on Cortex-R5F based Hercules devices (TMS570LC43x, and RM57Lx) is enabled by default. The ECC protection on Cortex-R4/R4F based Hercules devices (TMS570LSx, and RM4xLx) is disabled by default.

    On Cortex-R4 based Hercules devices, the ECC protection for accesses to the EEPROM emulation flash bank can be enabled by writing 0xA to the EE_EDACEN field of the flash module’s Error Correction Control Register 1 (EE_CTRL1).

    3. How can I enable the single and double bit Error Corrections?

    FEE software provides a mechanism to detect single and double bit errors. In order to use this feature, application has to make sure that “EE_EDACMODE[3:0]: Error Correction Mode” in “EE_CTRL1” should be set to a value other than 0101, “EE_ONE_EN: Error on One Fail Enable” should be enabled, “EE_ZERO_EN: Error on Zero Fail Enable” should be enabled, “EE_EDACEN[3:0]: Error Detection and Correction Enable” should be set to a value other than 0101.

    4. Is Checksum used for FEE block protection, and what is the Checksum algorithm used in FEE driver?

    Yes, CRC checksum is an option in FEE block header. If CRC is enabled, during writing of a block, CRC of the data to be written is calculated and checked against the CRC of the same block which is already existing in FEE Flash. If CRC matches, data is not written. If CRC is not enabled, then data is compared byte by byte. If data does not match, write will be initiated.

    The algorithm used in FEE driver is Fletcher-16 checksum.

    5. What is the weakness of Fletcher-16 checksum?

    The Fletcher-16 checksum cannot distinguish between blocks of all 0 bits and blocks of all 1 bits. For example, if a 16-bit block in the data word changes from 0x0000 to 0xFFFF, the Fletcher checksum remains the same. This also means a sequence of all 00 bytes has the same checksum as a sequence (of the same size) of all FF bytes.

    6. Can we call all the FEE APIs in USER mode?

    No. FEE needs following API’s to be executed in Privilege mode: TI_Fee_Init, and TI_FeeInternal_WriteDataF021

    7. Can I call TI_Fee_Init() API more than one time?

    No. TI_Fee_Init() provides functionality for initializing the TI FEE module. This routine must be called only once at the beginning before commencing any data operation.

    8. What happens if there is a RESET during flash is been erasing?

    In next initialization, this sector is added to the erase queue since sector header will not match with the expected sector header states (Active, Copy, Ready for Erase, Empty). Erasing will happen in the background.

    9. What happens if there is a RESET during writing data?

    Block is written in following way:

    • Block status is programmed as start program block.
    • Block number and block size are written.
    • Write data of the block.
    • After completion of writing of data, Checksum and address of previous block are written
    • Block status is marked as Active.

    If reset happens after step 1, then in next initialization, writing of next block is shifted by 24 bytes.

    If reset happens after step 2, step 3, step 4 or step 5, then the writing of next block will happen after current block size + block header.

    10. Can I run FEE operation in interrupt ISR?

    We strongly recommend not to use Flash Sync Operation (FEE Write especially) inside ISR. FEE write can initiate an Flash Erase operation during the Page Swap (i.e., if Virtual Sector is full and moves to different Virtual Sector and perform erase of old Virtual sector). which could take considerable amount of time and also it varied from device to device and with ageing too.

    You can initiate a Async Write (TI_Fee_WriteAsync) inside ISR and perform TI_Fee_Mainfunction outside of ISR. The actual write is performed in TI_Fee_MainFunction.