[FAQ] TMS570LC4357: What are the differences among the memory attributes, memory types and cache policy in MPU settings?

The Memory Protection Unit (MPU) is a programmable unit that allows privileged software, typically an OS kernel, to define memory access permission. It monitors transactions, including instruction fetches and data accesses from the processor, which can trigger a fault exception when an access violation is detected.

The ARM Cortex-R based MCUs have the three memory types: Normal, Device, and Strongly-ordered. The memory region have the following attributes:  shareable or non-shareable, cacheable or non-cacheable, memory access permission, and eXecute Never (XN).

The MPU registers need to be programmed and enabled before use. This is usually done in the initialization phase of any application running on the target MCU, after the system startup.

What are the MPU used for?

1. Prevent an untrusted application from accessing protected memory regions

2. Prevent user applications from corrupting data used by the operating system

3. Separate data between processing tasks by blocking tasks from accessing other data

4. Allow memory regions to be defined as read-only so that vital data can be protected

5. Detect unexpected memory access

What is the read allocate and write allocate in MPU settings?

Read Allocate.  All cacheable locations on ARM Cortex-R based MCUs are read allocate. This means that the data cache lines are allocated when a cache miss occurs, bringing data from the main memory into the cache memory. As a result, subsequent access to these memory locations will result in a cache hit condition, and the data is directly read from the cache memory.

Write Allocate:  On a cache miss, a cache line is allocated and loaded with the data from the main memory. This means that executing a store instruction on the processor might cause a burst read to occur to bring the data from the main memory to cache. No Write Allocate On a cache miss, a cache line is not allocated and the data is written directly into the main memory. Here, a line is not cached until a cache miss on a read occurs, which then loads the cache using the Read Allocate policy.

What are the procedures to setup up the MPU region?

1. Select the MPU region

2. Write the base address of the MPU region

3. Write the attributes of the MPU region

4. Enable MPU: SCTLR Register

What is the attribute of an overlapped region?

When memory regions overlap, memory access is affected by the attributes of the region with the highest number.

What is the difference between shareable and non-shareable memory?

The shareable means that the memory region is shared by several processors. The non-shareable means that the memory region is only used by a single processor. It has nothing to do with DMA access.

What is write back and write through in MPU settings?

Write-Back: On a cache hit, only the data cache is updated and not the main memory. The cache line is marked as dirty, and writes to the main memory are postponed until the cache line is evicted, or explicitly cleaned.

Write-Through: On a cache hit, both the data cache and the main memory are updated.

What does non-cacheable mean?

Each read and write is performed on the main memory, doesn’t go through the cache.

What are the differences among strongly-ordered, device, and normal memory?

-- Strongly-ordered (so) and Device (dev):

   1. Explicit load/stores to strongly-ordered and device regions always produce the exact size and number of transactions.

   2. Accesses to strongly-ordered and device regions always appear in the order they are listed in the program.

-- Strongly-ordered versus Device:

   1. Strongly-ordered access are ordered with respect to *all* other explicit load/stores.

   2. Device accesses are only ordered with respect to other device accesses

-- Normal (norm):

   1. Load/stores to normal memory regions may result in any size and number of transactions. For example: Two neighboring half-word stores might be merged into a single-word write. 

   2. With respect to ordering, accesses to normal memory may be reordered.

-- Examples:

   load-norm-A, load-dev-B, load-dev-C, load-norm-D could be performed as ADBC, or even DBCA;

   load-norm-A, load-so-B, load-so-C, load-norm-D must be performed as ABCD.