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AM2634-Q1: IPC multi-core communication cannot trigger an interrupt

Cherry Zhou
Mastermind 22235 points
Part Number: AM2634-Q1

Hi team,

Here's an issue from the customer may need your help:

The following issues occur when debugging the am263x IPC_notify feature: 

1) At the second step, the bit corresponding to the IPC register read_Req of Core 0 is set to 1, but Core0 does not enter an interrupt (Interrupt configuration has been tested with the function vimTriggerSoftInt and entry can be triggered, i.e. interrupt configuration is OK) .

2) After entering an interrupt, the interrupt flag bit needs to be cleared, specifically which register is cleared? The routines for the reference SDK are the clear flag bit write done. But in reality, it's read req.

Interrupt configuration is as follows:

Vim_IntCfg intCfg;
intCfg.map = VIM_INTTYPE_IRQ;
intCfg.type = VIM_INTTRIGTYPE_LEVEL;
intCfg.intNum = MSS_CR5A_MBOX_RD_REQ;
intCfg.handler = IPC_CoreReqHandle;
intCfg.priority = VIM_PRIORITY_3;
vimRegisterInterrupt(&intCfg);
vimEnableInterrupt(MSS_CR5A_MBOX_RD_REQ);

intCfg.map = VIM_INTTYPE_IRQ;
intCfg.type = VIM_INTTRIGTYPE_PULSE;
intCfg.intNum = MSS_CR5A_MBOX_RD_ACK;
intCfg.handler = IPC_CoreReqHandle;
intCfg.priority = VIM_PRIORITY_3;
vimRegisterInterrupt(&intCfg);
vimEnableInterrupt(MSS_CR5A_MBOX_RD_ACK);
 

Trigger Code: (The write to shared memory section is omitted, this function tells the target core to read the data after the shared memory has been written) 

void IPC_NotifyCoreWriteDown( uint32_t TarCore)
{
uint32_t mailboxBaseAddr, intrBitPos;
IpcNotify_SwQueue *swQ;
IPC_GetNotifyMailboxAddr(&TarCore, &mailboxBaseAddr, &intrBitPos, &swQ);

volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
*addr = (1<<intrBitPos);
}

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Intellectual 2085 points

    Hi Cherry,

    1) At the second step, the bit corresponding to the IPC register read_Req of Core 0 is set to 1, but Core0 does not enter an interrupt (Interrupt configuration has been tested with the function vimTriggerSoftInt and entry can be triggered, i.e. interrupt configuration is OK) .

    - Which core is writing to the write done register? Please make sure that sender core is writing to the WRITE DONE register dedicated to the core. Then the receiver core can read the READ REQ register to know which core triggered the interrupt.

    2) After entering an interrupt, the interrupt flag bit needs to be cleared, specifically which register is cleared? The routines for the reference SDK are the clear flag bit write done. But in reality, it's read req.

    - Interrupt flag bit can be cleared by writing to the READ REQ register. SDK also writes to READ REQ register for clearing the interrupt.

    Regards,

    Ashwin