• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 150 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C129XNCZAD: Boot loader on UART1

Rajesh Varma
Prodigy 250 points
Part Number: TM4C129XNCZAD

Dear Sir,

I am try to use boot loader  on UART1 for controller TM4C129XCNZAD

I want to use UART1 for update of code.

The PORT Use as PORTQ and pin 4  and Pin 5

// PQ4-5 are used for UART1.
ROM_GPIOPinConfigure(GPIO_PQ4_U1RX);
ROM_GPIOPinConfigure(GPIO_PQ5_U1TX);
ROM_GPIOPinTypeUART(GPIO_PORTQ_BASE, GPIO_PIN_4 | GPIO_PIN_5);

Initialization of UART1 as describe in Sample example. 

void Uart1_PC_init(uint32_t ui32SysClock)
{
MAP_GPIOPinTypeUART(GPIO_PORTQ_BASE, GPIO_PIN_4 | GPIO_PIN_5); 

MAP_UARTConfigSetExpClk(UART1_BASE, ui32SysClock, 9600,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));


MAP_IntEnable(INT_UART1);
MAP_UARTIntEnable(UART1_BASE, UART_INT_RX | UART_INT_RT);


}

The blconfig.h was modified for above  UART1 but not working.

I have some doubt that the setting done by myself have issue .

Can you check for UART1 for above configuration. Attached blconfig.h

7444.bl_config.h

Regards,

Rajesh Varma

  • 0
    TI__Guru**** 159085 points

    Hi,

      I think there is some issue with the RCGCGPIO register. Please see your below snippet of code. Please also refer to the datasheet for RCGCGPIO register for PortQ. As you can see in the datasheet, PortQ is mapped to R14, not R1. You need to change to R14 for both RX and TX pin for RCGCGPIO. 

    //*****************************************************************************
    //
    // Selects the clock enable for the GPIO corresponding to UART RX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_RXPIN_BASE, UART_RXPIN_PCTL and UART_RXPIN_POS
    //
    //*****************************************************************************
    #define UART_RXPIN_CLOCK_ENABLE SYSCTL_RCGCGPIO_R1

    //*****************************************************************************
    //
    // Selects the base address for the GPIO corresponding to UART RX pin
    //
    // Depends on: UART_ENABLE_UPDATE
    // Exclusive of: None
    // Requires: UART_RXPIN_CLOCK_ENABLE, UART_RXPIN_PCTL and UART_RXPIN_POS
    //
    //*****************************************************************************
    #define UART_RXPIN_BASE GPIO_PORTQ_BASE