TMS570LS0432: PLL under cycle slip causes CAN communication failure

Hi Will,

The probability of getting PLL slip is higher at low temperature. By default the PLL clock is configured by to automatically switch-over to the oscillator and the ESM/exception is generated in case of a PLL slip. In the exception service routine, you can disable then re-enable the PLL to lock the PLL.

A PLL slip may be configured to generate a system reset. Does the PLL get recovered after reset?

You can follow this procedure to disable and reenable the PLL in the exception service routine:

1. Switch all clock domains from PLL1 to the oscillator
2. Disable PLL1 with CSDISSET. This action disables the PLL and causes the slip signal to no longer be driven.
3. Clear the RFSLIP or FBSLIP status flags in GLBSTAT
4. Re-enable PLL1 with CSDISCLR.
5. Switch the clock domains back to PLL1.

To generate interrupt when PLL1 Slip occurs:

1. Make sure the BPOS=0x1, ROS=0 (PLLCTL1 register): OSC will be used after PLL slip, reset is not generated, but ESM flag is set (ESM 1.10 and ESM 1.42)

2. Enable ESM interrupt 

The ESM supports up to 128 channels which is divided into 3 groups. The Group 1 has 64 channels: channel 0 to channel 63. By default, the interrupt for channels in Group 1 is not enabled. To enable the interrupt for channel 10 and channel 42 of group 1 (ESM 1.10, ESM 1.42):

1. esmREG->IESR1 |= 0x1 << 10;  //ESM 1.10

    esmREG->IESR4 |= 0x1 << 10; //ESM 1.42   

    esmREG->ILSR1 &= ~(0x1 << 10); //Low level for ESM 1.10

    esmREG->ILSR4 &= ~(0x1 << 10); //Low level ESM interrupt for ESM 1.42

    You can do this step using HALCoGen:

2. Enable ESM interrupt in VIM module:

void esmLowInterrupt(void) will be generated in esm.c

3. Add code to esmGroup1Notification(..):

you can write your own code to disable PLL and re-enabled PLL. 

you can also call the functions generated by HALCOGen

a. _errata_SSWF021_45_pll1(...)

b. setupPLL();

c.  mapClocks();

Hi QJ, 

Thanks so much for your instruction. But in the failure board, even power-on reset can not save the device from the PLL under cycle slip. Not sure whether POR has similar effect as "disable and reenable the PLL " process ? If these two method are different, I will let them try the "disable and reenable the PLL " process. 

I also suggest customer that let the system work under low-frequency (20 MHz) operating condition, but they said that the whole system application may encounter with serious abnormal functions. 

What else workarounds can be used? Thanks. 

Best Regards, 

Will