TM4C123GH6PM: I2C slave mode sync / delay problem

Hello Ralph,

Is there an example on how to return NACK? Should I just set the ACKOVAL = 1 and ACKOEN = 1, ACKOEN to enable override, and ACJOVAL=1 to return a NACK?

Something like:

HWREG(I2C0_BASE + I2CSACKCTL) = ACKOVAL | ACKOEN

?

Best Regards,

Can

Hello Ralph,

I have added a:

void I2C0SlaveIntHandler(void) {

    // ACK override disable
    HWREG(I2C0_BASE + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN;

    HWREG(I2C0_BASE + I2C_O_SICR) = I2C_SICR_DATAIC;        // clear data interrupt

    if(HWREG(I2C0_BASE + I2C_O_SRIS) & I2C_SLAVE_INT_START) {
        HWREG(I2C0_BASE + I2C_O_SICR) = I2C_SICR_STARTIC;   // clear start interrupt
    } else if(HWREG(I2C0_BASE + I2C_O_SRIS) & I2C_SLAVE_INT_STOP) {
        HWREG(I2C0_BASE + I2C_O_SICR) = I2C_SICR_STOPIC;    // clear stop interrupt
        g_i2c_ready = true;
        return;
    }

    switch(I2CSlaveStatus(I2C0_BASE)) {
        case I2C_SLAVE_ACT_NONE:
            break;
        case I2C_SLAVE_ACT_RREQ_FBR:
            byteAddress = I2CSlaveDataGet(I2C0_BASE);
            switch(byteAddress) {
                case READ_STATUS:
                    if(busy) {
                        // ACK override enable
                        HWREG(I2C0_BASE + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN;
                        // send NACK
                        HWREG(I2C0_BASE + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL;
                    }
                    break;

So, when first byte is received, if it is read_status, I return a NACK.

It does work as expected, but when the busy status goes away, normal (non read_status) calls will return error, once or twice, then return to normal operations.

I think by sending NACK, we disturb the state of the i2c module. Basically I return NACK after clearing intterrupts. Should I be doing something else as well to reset the sate of the i2c module?

Best Regards,

Can

Hi Can,

I'd want to see the state of the I2C bus signals before really trying to give guidance here. Not sure if the master tries to do some sort of error recovery and maybe that's what's throwing things off, or if a NACK at that point is disrupting something. Also in general my lean on I2C is let the master fix any issues as I think its the master that should be driving error recovery. 

Best Regards,

Ralph Jacobi

Hello Ralph,

Here are I2C bus signals:

This is when I get the remote error(121). After that it gives connection timeout(110) for twice, and then 1 io error(5) and then it returns to normal operation.

Below i the whole shot

And here is the beginning of it zoomed:

and the end of it zoomed:

The SDA line stays low after error, and it is from tm4c123 side, (I have checked it by unplugging sda from master - and wiring the logic analyzer directly from slave tm4c123. after NACK is received, the master continues to do an address read.

I am using the linux kernels smbus module on a RPI4, tru python, so I dont have low level access to i2c master.

Best regards,

Can

The 123, 110, and 5 are error codes that the master returns. The master is on a RPI, and python smbus library is used for driving the linux kernel i2c module as master.

I am not sure if we can NACK the address read, since we dont have that state returned from 'I2CSlaveStatus(I2C0_BASE)'

How do we apply this NACK pattern? Do we send data byte, and then NACK? Should it be performed before and after putting data on the bus?

I am sure we are doing something wrong, and I have not been able to find any previously done samples in github nor google.

---

Meanwhile, I solved my sync problems by: using crc8 checksum for the 32 byte packet, and when status is read when device is making calculations, it will just return 0's for the data bytes, but proper checksum. Then I made a buffer, where I memcpy my calculation array to this buffer, which gets sent by the i2c slave.

Then I realized that the i2c read operation of 32bytes takes much more time then memcpying 32 bytes, so occasionally i get 0's in the byte array that gets sent.

Then I made a python routine that adjust the timer frequency such that the  i2c master will poll the i2c slave only 10ms after it makes its calculations, so I never hit the device when it will be busy.

I made a workaround, but without using NACK, but I still would like to know how to return NACK.

Best Regads,

Can

Hi Can,

Reading into this, I think I see the problem a little differently now. The idea of using a NACK to would hinge on knowing that the packet is one you need to packet ahead of time, and so you NACK the read request. Once you ACK the read request, if you need more time, you could try and implement clock stretching by having the I2C line get held down until you are ready to send data. But otherwise you'd need to know you'd be NACK'ing the read request before it arrives.

Sending a NACK on a data byte you transmit isn't covered by the I2C protocol from what I know:

There are five conditions that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge.

2. The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the master.

3. During the transfer, the receiver gets data or commands that it does not understand.

4. During the transfer, the receiver cannot receive any more data bytes.

5. A master-receiver must signal the end of the transfer to the slave transmitter.

Best Regards,

Ralph Jacobi