RM46L852: Enabling the ARM performance counter on TI Hercules MCU

Gabriel B

Part Number: RM46L852

Hi,

To my understanding, High-end ARM processors based on Cortex-A and Cortex-R include Performance Monitor Unit (PMU) which provides information like cycle counts.
Is there a way to activate this performance counter on the TI RM46?

Reference: ARM Cortex-R4 reference

Following this application note : https://www.ti.com/lit/fs/spna138a/spna138a.pdf?ts=1675176362803
I get the following

_pmuInit_();
_pmuEnableCountersGlobal_();
_pmuSetCountEvent_(pmuCOUNTER0, PMU_CYCLE_COUNT); // PMU_INST_ARCH_EXECUTED

_pmuResetCounters_();
_pmuStartCounters_(pmuCOUNTER0);
cycles_PMU_start = _pmuGetEventCount_(pmuCOUNTER0);

code_to_be_measured();

_pmuStopCounters_(pmuCOUNTER0);
cycles_PMU_end = _pmuGetEventCount_(pmuCOUNTER0);
cycles_PMU_measure = cycles_PMU_end - cycles_PMU_start;

That said, it doesn't appear to work when I put this code in sys_main.c: the cycles_PMU_measure is still at 0.

Any help is appreciated.

Best,
Gabriel

over 1 year ago

0 QJ Wang over 1 year ago

TI__Guru**** 186196 points

Hi Gabriel,

Please use cycle counter to count the PMU cycles:

    /*Reset Cycle Counter */
    _pmuResetCounters_();

    /*Start Cycle Counter */
    _pmuStartCounters_(pmuCYCLE_COUNTER);

    code_to_be_measured();

    /*Stop Cycle Counter */
    _pmuStopCounters_(pmuCYCLE_COUNTER);

    /* read the CNNT cycle */
    cycles= _pmuGetCycleCount_();

0 QJ Wang over 1 year ago

TI__Guru**** 186196 points

Please refer to my notes and example here:

https://software-dl.ti.com/hercules/hercules_docs/latest/hercules/Examples/Examples.html#using-performance-monitoring-unit-pmu-to-evaluate-code-efficiency

0 Gabriel B over 1 year ago in reply to QJ Wang

Intellectual 310 points

Hi QJ,

You're right, this is working! I guess the app note I found was outdated.

My only problem is that in UserMode (CPRS M: 10000), calling the _pmuGetCycleCount_ makes my MCU crash.
I assume it's because the MRC instruction is touching P15 (is this the same thing as CP15 ?) and P15 must be somewhere protected by the MPU.

Do you know where P15 is located in memory, I'm not finding it in the reference manual.

I just noticed that your guide mentions _pmuEnableUserMode_();
This is exactly what I need! The only problem, it doesn't appear to exist in my HalCoGen-generated sys_pmu.h.

Do you have the assembly for this function?

Thanks for your help,
Gabriel

+1 QJ Wang over 1 year ago in reply to Gabriel B

TI__Guru**** 186196 points

Gabriel B said:
is this the same thing as CP15 ?

Yes, p15 in the MRC/MCR instructions stands for CP15 registers.

The PMU registers are always accessible in Privileged mode. You can use the User Enable (PMUSERENR) Register to make all of the PMU registers, except for the Interrupt Enable Set (PMINTENSET), and Interrupt Enable Clear (PMINTENCLR) Registers, accessible in User mode.

Gabriel B said:
Do you know where P15 is located in memory, I'm not finding it in the reference manual.

It is not in ARM Cortex-R TRM: ARM DDI 0363C

https://developer.arm.com/documentation/ddi0363/g/Events-and-Performance-Monitor

Gabriel B said:
Do you have the assembly for this function?

You can download the example project from the link.

/* Enables User mode access to the PMU (must be called in a privileged mode)
 ***/
void _pmuEnableUserMode_(void)
{
    asm(" MRC     p15, #0, r0, c9, c14, #0"); //Read PMUSERENR Register
    asm(" ORR     r0, r0, #0x01");            //Set EN bit (bit 0)
    asm(" MCR     p15, #0, r0, c9, c14, #0"); //Write PMUSERENR Register
    asm(" ISB");                              //Synchronize context
}

0 Gabriel B over 1 year ago in reply to QJ Wang

Intellectual 310 points

Hi QJ,

I have done some tests, and this solves my problem completely.
Thanks for your time.

Best regards,
Gabriel

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RM46L852: Enabling the ARM performance counter on TI Hercules MCU