Hi experts,
Regarding MSPM0L1304SDYY, please confirm the following statement on P15 of the datasheet.
(1) Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE.
Ceramic capacitors have a tolerance on the rated capacitance, but apart from that, the capacitance change (%) due to temperature characteristics is also listed.
Is it correct to think that the capacitance change must be within 20% after taking into account not only the tolerance but also the capacitance change due to temperature characteristics?
Or is only the tolerance sufficient?
Best regards,
O.H
