EK-TM4C129EXL: Error in debugging, but code still works

Hello,

I am the original asker of this inquiry. The TI support that posted this for me did not include the attachments needed to see what my problem is. I am attaching the code variants that work and the snippet of what I am using that does not and the error message I am getting. I do not see how to add attachments, so I am adding the raw code. The raw code has what works immediately, despite the error and the 2nd code snippet has what is not.

The problem: Imgur: The magic of the Internet

#include <stdint.h>
#include <stdbool.h>

#define GPIO_PORTN ((volatile uint32_t *)0x40064000)
#define GPIO_PORTL ((volatile uint32_t *)0x40062000)
#define GPIO_PORTK ((volatile uint32_t *)0x40061000)
#define GPIO_PORTF ((volatile uint32_t *)0x4005D000)
#define SYSCTL ((volatile uint32_t *)0x400FE000)
#define SysTick ((volatile uint32_t *)0xE000E000)

#define SYSCTL_MOSCCTL_PWRDN (1 << 3)
#define SYSCTL_MOSCCTL_NOXTAL (1 << 2)
#define SYSCTL_MOSCCTL_OSCRNG (1 << 4)

#define SYSCTL_RIS_MOSCPUPRIS (1 << 8)

#define SYSCTL_MISC_MOSCPUMIS (1 << 8)

#define SYSCTL_RSCLKCFG_OSCSRC_MOSC (3 << 20)
#define SYSCTL_RSCLKCFG_PLLSRC_MOSC (3 << 24)
#define SYSCTL_RSCLKCFG_NEWFREQ (1 << 30)
#define SYSCTL_RSCLKCFG_PSYSDIV_M (0x3ff >> 0)
#define SYSCTL_RSCLKCFG_PSYSDIV_3 3
#define SYSCTL_RSCLKCFG_USEPLL (1 << 28)
#define SYSCTL_RSCLKCFG_MEMTIMU (1 << 31)

#define SYSCTL_PLLFREQ0_MINT_S 0
#define SYSCTL_PLLFREQ0_MFRAC_S 10
#define SYSCTL_PLLFREQ0_PLLPWR (1 << 23)

#define SYSCTL_MEMTIM0_EBCHT_M (0b1111 << 22)
#define SYSCTL_MEMTIM0_EWS_M (0b1111 << 16)
#define SYSCTL_MEMTIM0_EBCE (1 << 21)
#define SYSCTL_MEMTIM0_FBCHT_3_5 (6 << 6)
#define SYSCTL_MEMTIM0_EWS_6 (6 << 16)
#define SYSCTL_MEMTIM0_FBCHT_M (0b1111 << 6)
#define SYSCTL_MEMTIM0_FWS_M (0b1111 >> 0)
#define SYSCTL_MEMTIM0_FBCE (1 << 5)
#define SYSCTL_MEMTIM0_FWS_6 (6 >> 0)

#define GPIO_PIN_0 (1 >> 0)
#define GPIO_PIN_1 (1 << 1)
#define GPIO_PIN_2 (1 << 2)
#define GPIO_PIN_3 (1 << 3)
#define GPIO_PIN_4 (1 << 4)
#define GPIO_PIN_5 (1 << 5)
#define GPIO_PIN_6 (1 << 6)
#define GPIO_PIN_7 (1 << 7)

#define LED1_PN1 GPIO_PIN_1
#define LED2_PN0 GPIO_PIN_0
#define LED3_PF4 GPIO_PIN_4
#define LED4_PF0 GPIO_PIN_0

#define SYSCTL_RCGCGPIO_PORTF (1 << 5)
#define SYSCTL_RCGCGPIO_PORTL (1 << 10)
#define SYSCTL_RCGCGPIO_PORTK (1 << 9)
#define SYSCTL_RCGCGPIO_PORTN (1 << 12)

#define PUSH1_PL1 GPIO_PIN_1
#define PUSH2_PL2 GPIO_PIN_2

#define OUT_PK0 GPIO_PIN_0
#define OUT_PK1 GPIO_PIN_1
#define OUT_PK2 GPIO_PIN_2
#define OUT_PK3 GPIO_PIN_3

#define out (OUT_PK0 | OUT_PK1 | OUT_PK2 | OUT_PK3)

#define IN_PK4 GPIO_PIN_4
#define IN_PK5 GPIO_PIN_5
#define IN_PK6 GPIO_PIN_6
#define IN_PK7 GPIO_PIN_7

#define in (IN_PK4 | IN_PK5 | IN_PK6 | IN_PK7)

#define C 4778
#define D 4257
#define E 3792
#define G 3189

uint8_t index = 0;

const uint8_t sin[48] = {
0b0000,0b0000,0b0001,0b0001,0b0001,0b0010,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1101,0b1110,0b1110,0b1110,0b1111,0b1111,
0b1111,0b1111,0b1110,0b1110,0b1110,0b1101,0b1101,0b1100,0b1011,0b1010,0b1001,0b1000,0b0111,0b0110,0b0101,0b0100,0b0011,0b0010,0b0010,0b0001,0b0001,0b0001,0b0000,0b0000
};

enum {
SYSCTL_RCGCGPIO = (0x608 >> 2),
GPIO_DEN = (0x51c >> 2),
GPIO_DIR = (0x400 >> 2),
GPIO_PUR = (0x510 >> 2),
SYSCTL_MOSCCTL = (0x07C >> 2),
SYSCTL_RIS = (0x050 >> 2),
SYSCTL_MISC = (0x058 >> 2),
SYSCTL_RSCLKCFG = (0x0B0 >> 2),
SYSCTL_PLLFREQ0 = (0x160 >> 2),
SYSCTL_PLLFREQ1 = (0x164 >> 2),
SYSCTL_MEMTIM0 = (0x0C0 >> 2),
SYSCTL_PLLSTAT = (0x168 >> 2),
STCTRL = (0x010 >> 2),
STRELOAD = (0x014 >> 2),
STCURRENT = (0x018 >> 2),
PRI3 = (0xD20 >> 0)
};

void EnableInt(void);

void pll(void){
uint32_t tmp;

SYSCTL[SYSCTL_MOSCCTL] &= ~(SYSCTL_MOSCCTL_NOXTAL | SYSCTL_MOSCCTL_PWRDN);
if (!(SYSCTL[SYSCTL_MOSCCTL] & SYSCTL_MOSCCTL_OSCRNG)){
SYSCTL[SYSCTL_MOSCCTL] |= SYSCTL_MOSCCTL_OSCRNG;
while (!(SYSCTL[SYSCTL_RIS] & SYSCTL_RIS_MOSCPUPRIS));
}
SYSCTL[SYSCTL_MISC] = SYSCTL_MISC_MOSCPUMIS;
SYSCTL[SYSCTL_RSCLKCFG] |= SYSCTL_RSCLKCFG_OSCSRC_MOSC | SYSCTL_RSCLKCFG_PLLSRC_MOSC;
SYSCTL[SYSCTL_PLLFREQ0] = (96 << SYSCTL_PLLFREQ0_MINT_S) | (0 << SYSCTL_PLLFREQ0_MFRAC_S);
SYSCTL[SYSCTL_PLLFREQ1] = 4;

tmp = SYSCTL[SYSCTL_MEMTIM0];
tmp &= ~(SYSCTL_MEMTIM0_EBCHT_M | SYSCTL_MEMTIM0_EWS_M | SYSCTL_MEMTIM0_EBCE);
tmp |= SYSCTL_MEMTIM0_FBCHT_3_5 | SYSCTL_MEMTIM0_EWS_6;
tmp &= ~(SYSCTL_MEMTIM0_FBCHT_M | SYSCTL_MEMTIM0_FWS_M | SYSCTL_MEMTIM0_FBCE);
tmp |= SYSCTL_MEMTIM0_FBCHT_3_5| SYSCTL_MEMTIM0_FWS_6;
SYSCTL[SYSCTL_MEMTIM0] = tmp;

SYSCTL[SYSCTL_PLLFREQ0] |= SYSCTL_PLLFREQ0_PLLPWR;
SYSCTL[SYSCTL_RSCLKCFG] |= SYSCTL_RSCLKCFG_NEWFREQ;
while (!SYSCTL[SYSCTL_PLLSTAT]);

tmp = SYSCTL[SYSCTL_RSCLKCFG];
tmp = (tmp & ~SYSCTL_RSCLKCFG_PSYSDIV_M) | SYSCTL_RSCLKCFG_PSYSDIV_3;
tmp |= SYSCTL_RSCLKCFG_USEPLL | SYSCTL_RSCLKCFG_MEMTIMU;
SYSCTL[SYSCTL_RSCLKCFG] = tmp;
}

unsigned long piano(void){
unsigned long freq;

switch (GPIO_PORTK[in]){
case IN_PK4:
freq = C;
GPIO_PORTN[LED1_PN1] ^= LED1_PN1;
break;
case IN_PK5:
freq = D;
GPIO_PORTN[LED2_PN0] ^= LED2_PN0;
break;
case IN_PK6:
freq = E;
GPIO_PORTF[LED3_PF4] ^= LED3_PF4;
break;
case IN_PK7:
freq = G;
GPIO_PORTF[LED4_PF0] ^= LED4_PF0;
break;
default:
freq = 0;
break;
}

return freq - 1;
}

void DAC(uint8_t data){
GPIO_PORTK[out] = data;
}

void tone(unsigned long period){
SysTick[STRELOAD] = period;
}

void sysHand(void){
index = (index + 1) & 0x30;
DAC(sin[index]);
}

void main()
{
pll();

SysTick[STCTRL] = 0;
SysTick[STCURRENT] = 0;
SysTick[PRI3] = (0x4 << 28);
SysTick[STCTRL] = 0x7;

SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTN;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTF;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTL;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTK;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTN;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTF;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTL;
SYSCTL[SYSCTL_RCGCGPIO] |= SYSCTL_RCGCGPIO_PORTK;

GPIO_PORTN[GPIO_DIR] |= LED1_PN1;
GPIO_PORTN[GPIO_DEN] |= LED1_PN1;
GPIO_PORTN[GPIO_DIR] |= LED2_PN0;
GPIO_PORTN[GPIO_DEN] |= LED2_PN0;
GPIO_PORTF[GPIO_DIR] |= LED3_PF4;
GPIO_PORTF[GPIO_DEN] |= LED3_PF4;
GPIO_PORTF[GPIO_DIR] |= LED4_PF0;
GPIO_PORTF[GPIO_DEN] |= LED4_PF0;

GPIO_PORTL[GPIO_DIR] &= ~(PUSH1_PL1 | PUSH2_PL2);
GPIO_PORTL[GPIO_DEN] |= PUSH1_PL1 | PUSH2_PL2;

GPIO_PORTK[GPIO_DIR] &= ~in;
GPIO_PORTK[GPIO_DEN] |= in;

GPIO_PORTK[GPIO_DIR] |= out;
GPIO_PORTK[GPIO_DEN] |= out;

EnableInt();

while(true){
GPIO_PORTK[out] ^= out;
}
}

The code in the while loop that does not work (with a SysTick reload value hard coded): 

while(true){
GPIO_PORTK[out] = sin[index];
for (int i = 0;i < 1; i++)
while((SysTick[STCTRL] & 0x10000) == 0){}
index = (index + 1) & 0x30;
}

Thank you,

Drew

Hi,

  As stated in FAQ#4 https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/695568/faq-faqs-for-tm4c-arm-cortex-m4f-microcontrollers, we don't support DRM coding. I will suggest you single step your code and also my feedback (e.g. low-pass filter and using PWM module) on my last reply. 

Hello,

     I know you do not debug DRM code, but I was wondering if you knew of a solution to the errors in the image I sent: Imgur: The magic of the Internet

     I do not know what is happening since the console is saying that there is an error with port K, but port K appears to be working.

Thank you,

Drew

Hi,

The error message says you are reading registers at 0x400613fc. These are registers for GPIOK. You probably use the debugger to read these registers before GPIOK is enabled. You need to first enable GPIOK and then open the register or memory browser in CCS so that you don't get these errors. If you read any peripheral that is not yet enabled, the address decoder will report a bus error to the debugger. This is why you see the error message, 

Below link provides additional JTAG troubleshooting. 

software-dl.ti.com/.../ccs_debugging_jtag_connectivity_issues.html

Hello,

     Ah, that was the issue.  I was trying to read the expressions on GPIOK and they were not ready yet.  Alright, that solves that problem, now to fix my DAC issue.

Thank you,

Drew