TM4C1290NCPDT: EPI host mode cannot see write pin toggle on test board

With the following setup code, I start the EPI host

void epiPinoutSet(void)
{
    //
    // Enable all the GPIO peripherals.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT);

    //
    // Init. EPI0 Bus (General Purpose) (16 bits Data [0..15] + 12 bits Addr [16..27], WR[28], RD[29], FRAME[30], CLK[31])
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
    // Wait for GPIO change
    //while(SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0)){};
    // setup D8, D9
    GPIOPinConfigure(GPIO_PA6_EPI0S8); // pin 40 D8
    GPIOPinConfigure(GPIO_PA7_EPI0S9); // pin 41 D9
	GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);
	GPIOPinConfigure(GPIO_PB2_EPI0S27); // pin 91 A11
	GPIOPinConfigure(GPIO_PB3_EPI0S28); // pin 92 /WE (/rd hb16)
	GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
	GPIOPinConfigure(GPIO_PC4_EPI0S7); // pin 25 D8
	GPIOPinConfigure(GPIO_PC5_EPI0S6); // pin 24 D7
	GPIOPinConfigure(GPIO_PC6_EPI0S5); // pin 23 D6
	GPIOPinConfigure(GPIO_PC7_EPI0S4); // pin 22 D5
	GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
	GPIOPinConfigure(GPIO_PG0_EPI0S11); // pin 49 D11
	GPIOPinConfigure(GPIO_PG1_EPI0S10); // pin 50 D10
	GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);

	GPIOPinConfigure(GPIO_PH0_EPI0S0); // pin 18 D0
	GPIOPinConfigure(GPIO_PH1_EPI0S1); // pin 19 D1
	GPIOPinConfigure(GPIO_PH2_EPI0S2); // pin 20 D2
	GPIOPinConfigure(GPIO_PH3_EPI0S3); // pin 21 D3
	GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);

	GPIOPinConfigure(GPIO_PK5_EPI0S31); // pin 61 CLK
	GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);

	GPIOPinConfigure(GPIO_PL0_EPI0S16); // pin 22 D5
	GPIOPinConfigure(GPIO_PL1_EPI0S17); // pin 22 D5
	GPIOPinConfigure(GPIO_PL2_EPI0S18); // pin 22 D5
	GPIOPinConfigure(GPIO_PL3_EPI0S19); // pin 22 D5
	GPIOPinConfigure(GPIO_PL4_EPI0S26); // pin 22 D5
	GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);

	GPIOPinConfigure(GPIO_PM0_EPI0S15); // pin 22 D5
	GPIOPinConfigure(GPIO_PM1_EPI0S14); // pin 22 D5
	GPIOPinConfigure(GPIO_PM2_EPI0S13); // pin 22 D5
	GPIOPinConfigure(GPIO_PM3_EPI0S12); // pin 22 D5
	GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);

	GPIOPinConfigure(GPIO_PP2_EPI0S29); // pin    GPIO RD (HB16 /WR) 
	GPIOPinConfigure(GPIO_PP3_EPI0S30); // pin 22 D5
	GPIOPinTypeEPI(GPIO_PORTP_BASE, EPI_PORTP_PINS);

	// General Purpose Init
	EPIDividerSet(EPI0_BASE, 0x00000000);		// 0x00010001 1/2 (System) = 120MHz * 0.5 = 60MHz
	EPIModeSet(EPI0_BASE, EPI_MODE_HB16 );	// General Purpose
	EPIConfigHB16Set(EPI0_BASE, 
                       EPI_HB16_MODE_ADDEMUX | // sets up data and address as separate, D[15:0].
                       EPI_HB16_WRWAIT_0 |   // write wait 2 EPI clocks
                       EPI_HB16_RDWAIT_0 ,   // write wait 2 EPI clocks
                       0);
    
	EPIAddressMapSet(EPI0_BASE, 
                     EPI_ADDR_PER_SIZE_64KB | 
                     EPI_ADDR_PER_BASE_C  // set base to 0xC0000000
                     );
    }

I'd expect to see the write line toggle when I execute.

       volatile uint16_t *paddr=(uint16_t *)0xc0000010;
        while(1){ 
        *paddr=0x0005;
        delayms(1);
        *paddr=0x000A;
        delayms(1);
        }