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TMS570LS0914: Selecting Version B of eFuse Stuck at zero test using HalCoGen

Part Number: TMS570LS0914
Other Parts Discussed in Thread: HALCOGEN

Dear TI team,

I am using HalCoGen to generate self-test code for my platform. For the eFuse stuck at zero test, I wish to use the Version B of the stuck at zero test (because I don't want the ERROR pin set to low).

 eFuse stuck at zero test, reference manual

In HalCoGen, I can see where to enable eFuse self-test but I haven't found a way to choose the version B of eFuse stuck at zero test. Is there a way to choose the version B of stuck at zero test through HalCoGen?

Enable EFUSE self test in halcogen

Best regards,

Elieva

  • Hi Elieva,

    Unfortunately, HALCoGen will not have that setting to generate the code for Version B Efuse Stuck at zero test. It can only generate the Version A code by default.

    The only way here is to comment the version A code and have to write our own code for version B.

    I just modified my self the version A code and created version B code for your testing. Here it is:

    boolean efcStuckZeroTest(void)
    {
    /* USER CODE BEGIN (29) */
    /* USER CODE END */
    
        uint32 ESM_ESTATUS4;
    
        boolean result = FALSE;
        uint32 error_checks = EFC_INSTRUCTION_INFO_EN  |
                                      EFC_INSTRUCTION_ERROR_EN |
                                      EFC_SELF_TEST_ERROR_EN   ;
    
        /* configure the output enable for auto load error , instruction info,
             instruction error, and self test error using boundary register
             and drive values one across all the errors */
        efcREG->BOUNDARY = ((uint32)OUTPUT_ENABLE | error_checks);
    
        /* Read from the pin register. This register holds the current values
             of above errors. This value should be 0x5800.If not at least one of
             the above errors is stuck at 0. */
        if ((efcREG->PINS & 0x5800U) == 0x5800U)
        {
            ESM_ESTATUS4 = esmREG->SR4[0U];
    		
            /* check if the ESM group1 channel 41 is set*/
            if ((ESM_ESTATUS4 & 0x200U) == 0x200U)
            {
               /* stuck-at-zero test passed */
               result = TRUE;
            }
        }
    
        /* put the pins back low */
        efcREG->BOUNDARY = OUTPUT_ENABLE;
    
        /* clear group1 flag */
        esmREG->SR4[0U] = 0x200U;
    
        /* The nERROR pin will become inactive once the LTC counter expires */
        esmREG->EKR = 0x5U;
    
        return result;
    }

    --
    Thanks & regards,
    Jagadish.