Other Parts Discussed in Thread: AB15
Tool/software:
Hello
I am having an issue with the initialization of the EPI bus. The BUS is being configured to access two memory devices.
What I am seeing is on initialization of the EPI bus, I am getting a write enable signal and a chip select active signal which is resulting in unwanted writes to the device.
Yet, there have been no attempts to actually perform a write to the device.
See the diagram Write Enable Pulse (WR_ENn, Pin PN2)
Chip select CS_1n MRAM.
This is the code for the EPI initialization function, when this is called at startup the above events are triggered, result in an unwanted write to the device.
I am doing something wrong here.
int EPI_TCPIP_init(void)
{
int status = 1;
/* Enable the clock to the GPIO Ports that are required for EPI */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
/* EPI Pin assignments as per the HW/SW ICD */
MAP_GPIOPinConfigure(GPIO_PH0_EPI0S0);
MAP_GPIOPinConfigure(GPIO_PH1_EPI0S1);
MAP_GPIOPinConfigure(GPIO_PH2_EPI0S2);
MAP_GPIOPinConfigure(GPIO_PH3_EPI0S3);
MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19);
MAP_GPIOPinConfigure(GPIO_PQ0_EPI0S20); // PLD Memory AB15
MAP_GPIOPinConfigure(GPIO_PQ1_EPI0S21); // PLD Memory AB16
MAP_GPIOPinConfigure(GPIO_PQ2_EPI0S22); // PLD Memory AB17
MAP_GPIOPinConfigure(GPIO_PQ3_EPI0S23); // PLD Memory AB18
MAP_GPIOPinConfigure(GPIO_PK7_EPI0S24); // EPI_BSEL0n
MAP_GPIOPinConfigure(GPIO_PK6_EPI0S25); // EPI_BSEL1n
MAP_GPIOPinConfigure(GPIO_PL4_EPI0S26); // EPI_CS0n (FPGA). mapped to address range 0x60000000
MAP_GPIOPinConfigure(GPIO_PB2_EPI0S27); // EPI_CS1n (MRAM). mapped to address range 0x
MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28); // EPI_RDn
MAP_GPIOPinConfigure(GPIO_PN2_EPI0S29); // EPI_WRn
MAP_GPIOPinConfigure(GPIO_PN3_EPI0S30); // EPI_ALE
// the following signals are routed to the PLD nut not planned to be used
MAP_GPIOPinConfigure(GPIO_PK5_EPI0S31); // EPI_CLK*
MAP_GPIOPinConfigure(GPIO_PK4_EPI0S32); // EPI_iRDY*
MAP_GPIOPinConfigure(GPIO_PL5_EPI0S33); // EPI_CS3*
MAP_GPIOPinConfigure(GPIO_PN4_EPI0S34); // EPI_CS2*
MAP_GPIOPinConfigure(GPIO_PN5_EPI0S35); // EPI_CRE*
MAP_GPIOPinTypeEPI(GPIO_PORTA_BASE, (GPIO_PIN_7 | GPIO_PIN_6));
MAP_GPIOPinTypeEPI(GPIO_PORTB_BASE, (GPIO_PIN_3 | GPIO_PIN_2 ));
MAP_GPIOPinTypeEPI(GPIO_PORTC_BASE, (GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4));
MAP_GPIOPinTypeEPI(GPIO_PORTG_BASE, (GPIO_PIN_1 | GPIO_PIN_0));
MAP_GPIOPinTypeEPI(GPIO_PORTH_BASE, (GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0));
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, (GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4));
MAP_GPIOPinTypeEPI(GPIO_PORTL_BASE, (GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0));
MAP_GPIOPinTypeEPI(GPIO_PORTM_BASE, (GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0));
MAP_GPIOPinTypeEPI(GPIO_PORTN_BASE, (GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2));
/* Enable the clock to the EPI and wait for it to be ready */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
while(!(MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0)))
{
}
/* Configure the EPI to access the MRAM memory at 120 MHz Set the EPI clock to the system clock for MRAM (120MHz),
* and one quarter of the system clock for FPGA(30Mhz) */
EPIDividerSet(EPI0_BASE, 3);
// EPIDividerSet(EPI0_BASE, 0x00030003); // slower clock 30Mhz, still corruption
// Host-bus 16-bit interface
EPIModeSet(EPI0_BASE, EPI_MODE_HB16);
// HB16 settings as per ICD to allow for individual configurations
// of PLD Memory (CS0) and MRAM (CS1)
EPIConfigHB16Set(EPI0_BASE,
(EPI_HB16_MODE_ADMUX |
EPI_HB16_IN_READY_EN |
EPI_HB16_BSEL |
EPI_HB16_CSCFG_ALE_DUAL_CS |
EPI_HB16_CSBAUD),
8); //PF was 0
// Configuration for CS0, FPGA interface, refer to the ICD, FPGA Works
EPIConfigHB16CSSet(EPI0_BASE, 0,
(EPI_HB16_MODE_ADMUX |
EPI_HB16_WRWAIT_0 |
EPI_HB16_RDWAIT_0 |
EPI_HB16_ALE_HIGH));
// Configuration for CS1, MRAM interface, refer to the ICD
EPIConfigHB16CSSet(EPI0_BASE, 1,
(EPI_HB16_MODE_ADMUX |
EPI_HB16_WRWAIT_1 |
EPI_HB16_RDWAIT_1 |
EPI_HB16_ALE_HIGH));
EPIAddressMapSet(EPI0_BASE, ((EPI_ADDR_RAM_BASE_6 | EPI_ADDR_RAM_SIZE_16MB) | (EPI_ADDR_PER_BASE_A | EPI_ADDR_PER_SIZE_16MB)));
/*** adjust the MRAM wait states, reduce both read and write by 1 wait state ****/
//EPIConfigHB16TimingSet(EPI0_BASE, 1, (EPI_HB16_RDWAIT_MINUS_ENABLE | EPI_HB16_WRWAIT_MINUS_ENABLE));
//EPIConfigHB16TimingSet(EPI0_BASE, 1, EPI_HB16_RDWAIT_MINUS_ENABLE);
//EPIConfigHB16TimingSet(EPI0_BASE, 1, EPI_HB16_WRWAIT_MINUS_ENABLE);
/* Wait for the wake-up to complete by polling the
* initialization sequence bit. This bit is true when the SDRAM interface
* is going through the initialization and false when the SDRAM interface
* it is not in a wake-up period. */
while(EPI0->STAT & EPI_STAT_INITSEQ)
{
}
return(status);
}
Thanks In Advance.
Perry
