MSP432E401Y: MSP432E401Y SSIDATAGET() delay

zhonghai wang

Part Number: MSP432E401Y
Other Parts Discussed in Thread: ADS8329

Tool/software:

Hi Masters,

I am reading data from an ADC with the following code.

SSIConfigSetExpClk(SSI0_BASE, systemClock, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 30000000, 16);
//
// Enable the SSI module.
//
SSIEnable(SSI0_BASE);

//Read residual data in the FIFO
while (SSIDataGetNonBlocking(SSI0_BASE, &sample_data[0]))
{ }

for (i=0; i<N_sample; i++)
{
// manual trigger a sampling, /CONVST low for at least 40ns
GPIOPinWrite ( GPIO_PORTF_BASE, GPIO_PIN_4, 0 );
GPIOPinWrite ( GPIO_PORTF_BASE, GPIO_PIN_4, GPIO_PIN_4 );
SSIDataPut(SSI0_BASE,i);
SSIDataGet(SSI0_BASE, &sample_data[i]);
while(SSIBusy(SSI0_BASE))
{ }
}

There is a delay between neighboring SSIDATAGET(). As I use 30MHz SSI clock, I get a reading period of 2.06us (the delay is 1.52us), if I use a 40MHz SSI clock, the reading period is 1.789us (the delay is 1.48us).

Is it possible to reduce the delay and increase the reading rate?

Thanks a lot,

Zhonghai

2 months ago

0 Charles Tsai 2 months ago

TI__Guru**** 177666 points

Hi,

I will suggest you first set PF4 high before while(SSIBusy(SSI0_BASE)) and then clear the pin after while(SSIBusy(SSI0_BASE)). This measures the time it takes to transmit the 16 bits at your specified SSICLK frequency. If the PF4 duration is about 1.52us then it means it this is the required amount of time to transmit the data. You can't really shorten it any further. Of course you can remove the GPIOPinWrite totally in your while loop because it takes some cycles to execute the two GPIOPinWrite function calls. Removing it will shorten your read period. Instead of using PF4 to measure the read period, you can use the scope to measure time from the first SSICLK edge of the current data to the next first SSICLK edge of the next data.

0 zhonghai wang 2 months ago in reply to Charles Tsai

Prodigy 110 points

Dear Charles,

PF4 is used to trigger the ADC (TI ADS8329) for a conversion （please see the first attached figure）. As I removed the set and clear of PF4, the delay reduced to about 980ns. May I use the SSI port's FSS signal as the conversion trigger signal for the ADS8329?

Another issue I found is the delay between neighboring data reading frame is different as shown in the following figures.

The first two links show the reading frame time 2.5us (#1 link) and 2.47us (#2 link) for two reading period without set and clear PF4.

The last two links show the reading frame time 3.84us (#3 link) and 4.04us (#4 link) for two reading period with set and clear PF4.

www.dropbox.com/.../20241021_1.jpg

www.dropbox.com/.../20241021_2.jpg

www.dropbox.com/.../20241021_3.jpg

https://www.dropbox.com/scl/fi/qwuoiifdf2as9yfkqqx7w/20241021_4.jpg?rlkey=kl9k8mlrvh7lfdynscm8qtix9&dl=0

Is this normal for SSI port communication - each time the reading delay is different?

My initial design is to use the SSI port reading to trigger the ADC and control the ADC sampling rate. If this is true (the SSI port reading delay is not fixed from time to time), I need to revise my design.

Thank you very much,

Zhonghai

0 Charles Tsai 2 months ago in reply to zhonghai wang

TI__Guru**** 177666 points

Hi Zonghai,

I'm not an expert for ADS8329 as I support only the MCU. I don't think there would be an issue to use FSS for CONVST. It would be good that you open a new thread for ADS8329 so the experts supporting this device can confirm about the timing requirements.

BTW, I can't open the pictures you store at Dropbox as my company blocks access to any online cloud storage.

0 zhonghai wang 2 months ago in reply to Charles Tsai

Prodigy 110 points

Dear Charles,

Thank you very much. I will open a new thread for the ADS8329.

Please see the attached figures. I changed the figure size and kept the measurement results. The first two do not include set and clear PF4, the difference is 2.5us-2.47us=0.03us. The last two include set and clear PF4, the difference is 4.04us-3.84us=0.2us. Is this （the delay between neighboring reading frames is different) normal or not normal for an SSI port?