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TMS570LS3134: DMA SCI RX TX in full duplex

Ahmet KÜRKLÜ
Prodigy 40 points
Part Number: TMS570LS3134

Tool/software:

Hello,

I am working on a project where i will receive different messages from another MCU using the SCI. The messages have different length and I wont be able to know wich message will be sent in advance. I decided to implement the SCI RX using the DMA, I configured my channel like so :

g_dmaCTRL g_dmaCTRLPKT1;
dmaReqAssign(DMA_CH0,DMA_SCI2_RX);
/*Configure control packet for Channel 0*/

g_dmaCTRLPKT1.SADD = (uint32_t)((uint8*)&(scilinREG->RD)+3); /* source address*/
g_dmaCTRLPKT1.DADD = (uint32_t)dma_rx_buf; /* destination address */
g_dmaCTRLPKT1.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT1.FRCNT = BUFFER_SIZE; /* frame count */
g_dmaCTRLPKT1.ELCNT = 1; /* element count */
g_dmaCTRLPKT1.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.PORTASGN = 4;
g_dmaCTRLPKT1.RDSIZE = ACCESS_8_BIT; /* read size */
g_dmaCTRLPKT1.WRSIZE = ACCESS_8_BIT; /* write size */
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER; /* transfer type */
g_dmaCTRLPKT1.ADDMODERD = ADDR_FIXED; /* address mode read */
g_dmaCTRLPKT1.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_ON; /* autoinit */

dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT1);

dmaSetChEnable(DMA_CH0, DMA_HW);

dmaEnable();

With this configuration my dma_rx_buf buffer is filled with RX data and I use a function in my main loop to parse the message and then handle them.I wanted to add another channel to my DMA but I had a question. The priority is configured to work in Rotation and with how i configured my CHN0 the task will not end until 1000 byte is received. The second channel was supposed to handle the transfer of data from a buffer to the TX line of the SCI. If i understood correctly I saw in the datasheet that the DMA had only one port so if i want to transmit with the CHN1 i will have to stop the CHN0 and both these channel cant transmit data at the same time ? 

  • +1
    TI__Guru 57230 points

    Hi Ahmet,

    Ahmet KÜRKLÜ said:
    If i understood correctly I saw in the datasheet that the DMA had only one port so if i want to transmit with the CHN1 i will have to stop the CHN0 and both these channel cant transmit data at the same time ? 

    You are correct and this device have only one port for DMA. So it is not possible to handle two channels simultaneously. However, there is a two priority schemes available and i will explain these priority schemes in detailed in next comment.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 57230 points

    Hi Ahmet,

    Basically, there are two priority queues will be there in this DMA module. One is high priority queue and other is low priority queue. And each channel can be configured to be in one of these two queues.

    The pending channels in the lower priority queue will only handle when there are no pending channels in higher priority queue. This is the basic functionality for dividing two queues.

    And now we can operate each queue in either fixed priority scheme or rotating priority scheme independently.

    Fixed priority:

    In this priority scheme, the lower channel number have higher priority. That means if two channels are in pending then the lower channel number will execute first and then the higher channel number will get execute. The higher channel number should wait until the lower channel number finishes its task.

    Example:

    As mentioned earlier the low priority queue pending channels will only execute when there are no pending channels in the high priority queue. And now according to fixed priority scheme the lower channel have higher priority and higher channel have lower priority within the queue.

    Based on above two rules you can understand how the channels will be handled in fixed priority scheme.

    Rotating priority:

    In this scheme the pending channels are executed in round-robin manner. And there is no fixed priority here, so the channels will just execute in round robin manner, and the control to the next channel will be shift when FIFO for current channel is empty.

    That means the DMA have a FIFO, so using this FIFO it will transfer data from source to destination. Each pending channel data will be moved to this FIFO and the current channel data shift will happen until this FIFO gets empty. Once this FIFO empty then the current channel is arbitrated, and next pending channel will get opportunity, and the current arbitrated channel will get opportunity again after all the pending channels also shift the data of size equal to FIFO.

     

    In this way all channels will be executed in round-robin.

    Example:

    And here also the low priority queue pending channels will execute only if there were no pending channels in high priority queue.

    So may be for your requirement you can choose round robin scheme. So that both transmission and reception can get equal priority.

    --
    Thanks & regards,
    Jagadish.