Tool/software:
In my project I want to verify that the 200MHz SYS_CLK drives the IEP peripheral.
In the reference manual "7.3.12.2.1 PRU-ICSS IEP Clock Generation" it says the following.
The IEP has a selectable module input clock (PRU_ICSS_IEP_CLK, see also PRU-ICSS in Module Integration).
The clock source is selected by the state of the CTRLMMR_PRU_ICSS_CLKSEL[19-16] IEP_CLKSEL bit within
the CTRL_MMR0
I see that PRU_ICSS_IEP_CLK is driven by SYS_CLK through a gate. I want to read out CTRLMMR_PRU_ICSS_CLKSEL:IEP_CLKSEL to verify the clock source, but I can't find it in the register addendum.
Could you please advise on how to verify the PRU IEP clock source?
