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TM4C123GH6PM: PWM Triggering ADC module - on both middle of pwm high and pwm low

can altineller
Expert 1760 points

Part Number: TM4C123GH6PM

Hello,

I am using PWM module 0, Generator 0, to generate 2 pwm signals but from the same generator.

And I am triggering ADC on the middle of the PWM high with:

MAP_PWMGenIntTrigEnable(PWM0_BASE, PWM_GEN_0, PWM_TR_CNT_LOAD);

And:


MAP_ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_PWM0, 0);        
MAP_ADCSequenceConfigure(ADC0_BASE, 2, ADC_TRIGGER_PWM0, 1);

Which right now works. But I also would like to trigger adc when counter hits zero, so the adc triggers on both on the middle of on time and off time.

I can MAP_PWMGenIntTrigEnable(PWM0_BASE, PWM_GEN_0, PWM_TR_CNT_LOAD | PWM_TR_CNT-ZERO) ;


to trigger events for both zero and load values, effectively triggering adc - but is there any way to know which one is which? Right now we are using a trigger, so it will go to adc tru hardware. 

I understand we can create CMPA and CMPB to trigger interrupts which later will processor trigger adc. But given the high frequency of pwm, I would like to avoid this. Is there any way we can distinguish triggers, so I can attach different adc sequences  to them. I have read datasheets, tiva-c software manuals, and source code. and I think the answer is no, but still decided to ask to forum.

MAP_ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_PWM0, 0);

We need a way to configure sequence with triggers from pwm0 but different type of triggers.

 

Best Regards,

C.

  • 0
    Expert 1760 points

    Hello,

    I have made a method, where I read PMW_O_0_RIS and then check for PWM_0_RIS_INTCNTLOAD or PWM_0_RIS_INTCNTZERO.
    I also clear these by writing to HWREG(PWM0_BASE + PWM_O_0_ISC) = PWM_0_RIS_INTCNTLOAD;

    It does work, but I am not sure if I can intervene with PWM generators interrupt status like this. If ISR not cleared, it does not work.

    I wonder if this method could have some effects.

    Best Regards,

    C.

    void ADC0SS1IntHandler(void) {
  PWM_RIS = HWREG(PWM0_BASE + PWM_O_0_RIS);
  MAP_ADCIntClear(ADC0_BASE, 1);
  if(PWM_RIS & PWM_0_RIS_INTCNTLOAD) {
    HWREG(PWM0_BASE + PWM_O_0_ISC) = PWM_0_RIS_INTCNTLOAD;
    MAP_ADCSequenceDataGet(ADC0_BASE, 1, adc_fifo_right_load);
    adc_ss1_load_flag = true;
  } else if(PWM_RIS & PWM_0_RIS_INTCNTZERO) {
    HWREG(PWM0_BASE + PWM_O_0_ISC) = PWM_0_RIS_INTCNTZERO;
    MAP_ADCSequenceDataGet(ADC0_BASE, 1, adc_fifo_right_zero);
    adc_ss1_zero_flag = true;
  }
}