TMS570LS0914: SPI communication issue with AUTOSAR_MCAL_TMS570LSx-05.40.00

Renan Santos Adriano

Mastermind 25405 points

Part Number: TMS570LS0914
Other Parts Discussed in Thread: HALCOGEN

Hello Experts,

We are trying to communicate between TMS570LS0914 and QCA7006 through SPI_1.

RegistersBareMetal (1).txt

Autosar_SPI_MCAL.txt

With bare metal SW (halcogen generated SPI MCAL), we are able to get the desired resposne 0xAA55 by reading signature register 0x1A00 (Tx command : 0xDA00). As per the QCA7006 datasheet SPI should work in Mode 3 but actually we got the desired output for Mode 2 instead of Mode 3.

2. But as per our application, we have to use AUTOSAR MCAL. So, with AUTOSAR SPI MCAL we are not getting desired response for the same Tx command. Sometime we are getting 0xAAAA or 0x5555 as response.

Logic Analyzer Output.png

3. Registers dump of MibSpi1 for BareMetal SW as well as AUTOSAR MCAL integrated SW are attached here.

4. Please provide guidance to proceed further.

Regards,

Ushan Kumari

5 months ago

0 QJ Wang 5 months ago

TI__Guru**** 200126 points

Hi Ushan,

The HalCoGen generated SPI driver works as expected, but MCAL SPI driver doesn't work which interprets 0xAA55 (expected RX data) to 0xAAAA or 0x5555.

From the attached files, the TMS570 acts as a SPI master when using HalCOGen SPI driver, but it is configured as a slave when using MCAL SPI driver.

The POL=1, and Phase=0 which mean that the data is output on leading edge (falling) and input data is latched on the trailing edge (rising) -- Mode 2

Does another device (QCA7006) use mode 3 (POL=1 and Phase=1)? I think both should use the same mode.

0 Usha Kumari 5 months ago in reply to QJ Wang

Prodigy 60 points

Hi Wang,

Thanks for your response!!

Now we have configured the SPI driver (TMS570) as Master but still we are not receiving the correct response (0xAA55).

New register dump of AUTOSAR SPI MCAL has been attached here. Now we have configured SPI for Mode 3 as QCA7006 support SPI Mode 3.

Fullscreen MibSpi1.txt Download

			
Core Registers		Core Registers	
USER_Registers			
FIQ_Registers			
Supervisor_Registers			
Abort_Registers			
IRQ_Registers			
Undefined_Registers			
All_Banked_Registers			
Debug_Registers			
System_Registers			
Cp15			
Vfp			
MibAdc2			
MibAdc1			
Dcan3			
Dcan2			
Dcan1			
ePWM1			
ePWM2			
ePWM3			
ePWM4			
ePWM5			
ePWM6			
ePWM7			
eCAP1			
eCAP2			
eCAP3			
eCAP4			
eCAP5			
eCAP6			
eQEP1			
eQEP2			
Gio			
	GlbCtrl	0x00000001	Global Control Register [Memory Mapped]	
	PwDn	0x00000000	Power Down [Memory Mapped]	
	IntDet	0x00000000	Interrupt Detect [Memory Mapped]	
	IntPol	0x00000000	Interrupt Polarity [Memory Mapped]	
	IntEnaSet	0x00000000	Interrupt Enable Set [Memory Mapped]	
	IntEnaClr	0x00000000	Interrupt Enable Clear [Memory Mapped]	
	IntLvlSet	0x00000000	Interrupt Priority Set [Memory Mapped]	
	IntLvlClr	0x00000000	Interrupt Priority Clear [Memory Mapped]	
	IntFlg	0x0000FA10	Interrupt Flag [Memory Mapped]	
	OffstA	0x00000000	Offset A [Memory Mapped]	
	OffstB	0x00000000	Offset B [Memory Mapped]	
	EmuA	0x00000000	Emulation A [Memory Mapped]	
	EmuB	0x00000000	Emulation B [Memory Mapped]	
GioA			
	Dir	0x00000014	Data Direction Gio A [Memory Mapped]	
	DIn	0x0000000E	Data Input Gio A [Memory Mapped]	
	DOut	0x00000004	Data Output Gio A [Memory Mapped]	
	DSet	0x00000004	Data Set Gio A [Memory Mapped]	
	DClr	0x00000004	Data Clear Gio A [Memory Mapped]	
	PDr	0x00000000	Open Drain Gio A [Memory Mapped]	
	PDis	0x00000000	Pull Disable Gio A [Memory Mapped]	
	PSel	0x0000009E	Pull Select Gio A [Memory Mapped]	
	Srs	Error: unable to read	Slew Rate Select Gio A [Memory Mapped]	
GioB			
I2C			
Nhet1			
	GlbCtrl	0x00030001	global control register [Memory Mapped]	
	Pfr	0x00000700	prescaler factor register [Memory Mapped]	
	Addr	0x00000000	Current Address Register [Memory Mapped]	
	Offst1	0x00000000	Offset Level 1 Register [Memory Mapped]	
	Offst2	0x00000000	Offset Level 2 Register [Memory Mapped]	
	IntEnaSet	0x00000000	Interrupt Enable Set Register [Memory Mapped]	
	IntEnaClr	0x00000000	Interrupt Enable Clear Register [Memory Mapped]	
	Exc1	0x00000000	Exception Control Register 1 [Memory Mapped]	
	Exc2	0x00000000	Exception Control Register 2 [Memory Mapped]	
	IntPrio	0x0000FFFF	Interrupt Priority Register [Memory Mapped]	
	IntFlg	0x00000002	Interrupt Flag Register [Memory Mapped]	
	HrSh	0x00000000	HR Share Control Register [Memory Mapped]	
	Xor	0x00000000	HR Xor control register [Memory Mapped]	
	ReqEnaSet	0x00000000	Request Enable Set Register [Memory Mapped]	
	ReqEnaClr	0x00000000	Request Enable Clear Register [Memory Mapped]	
	ReqDst	0x00000000	Request Destination Select Register [Memory Mapped]	
	Dir	0x40C40380	Direction Register [Memory Mapped]	
	DIn	0xBF2BE05D	Input Data Register [Memory Mapped]	
	DOut	0x02024000	Output Data Register [Memory Mapped]	
	DSet	0x02024000	Set Data Register [Memory Mapped]	
	DClr	0x02024000	Clear Data Register [Memory Mapped]	
	PDr	0x00000000	Open Drain Register [Memory Mapped]	
	PDis	0x00000000	Pull Disable Register [Memory Mapped]	
	PSel	0xFF7FFFFF	Pull Select Register [Memory Mapped]	
	ParCtrl	0x00000005	Parity Control Register [Memory Mapped]	
	ParAddr	0x00000000	Parity Address Register [Memory Mapped]	
	ParPinReg	0x00000000	Parity Pin Register [Memory Mapped]	
	SfPrld	0x00000000	Suppresion Filter Preload Register [Memory Mapped]	
	SfEna	0x00000000	Suppresion Filter Enable Register [Memory Mapped]	
	LbPairSel	0x00000000	Loop Back Pair Select Register [Memory Mapped]	
	LbPairDir	0x00050000	Loop Back Pair Direction Register [Memory Mapped]	
	PinDis	0x00000000	Pin Disable Register [Memory Mapped]	
	HWAGCR0	0x00000000	HWAG Control Register 0 [Memory Mapped]	
	HWAGCR1	0x00000000	HWAG Control Register 1 [Memory Mapped]	
	HWAGCR2	0x00000000	HWAG Control Register 2 [Memory Mapped]	
	HWAENASET	0x00000000	HWAG Interrupt Enable Set Register [Memory Mapped]	
	HWAENACLR	0x00000000	HWAG Interrupt Enable Clear Register [Memory Mapped]	
	HWALVLSET	0x00000000	HWAG Interrupt Priority Set Register [Memory Mapped]	
	HWALVLCLR	0x00000000	HWAG Interrupt Priority Clear Register [Memory Mapped]	
	HWAFLG	0x00000000	HWAG Interrupt Flags Register [Memory Mapped]	
	HWAOFF0	0x00000000	HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset [Memory Mapped]	
	HWAOFF1	0x00000000	HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset [Memory Mapped]	
	HWAACNT	0x00000000	HWAG ACNT Register, HWAG Angle Value [Memory Mapped]	
	HWAPCNT1	0x00000000	HWAG PCNT (n-1) Register, HWAG Previous Tooth Period [Memory Mapped]	
	HWAPCNT	0x00000000	HWAG PCNT (n) Register, HWAG Current Tooth Period [Memory Mapped]	
	HWASTWD	0x00000000	HWAG Step Register [Memory Mapped]	
	HWATHNB	0x00000000	HWAG Teeth Number Register [Memory Mapped]	
	HWATHVL	0x00000000	HHWAG Current Teeth Number Register [Memory Mapped]	
	HWAFIL	0x00000000	HWAG Filter Register, HWAG Tick Counter Compare Value [Memory Mapped]	
	HWAFIL2	0x00000000	HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth [Memory Mapped]	
	HWAANGI	0x00000000	HWAG Angle Increment Register [Memory Mapped]	
Nhet2			
Htu1			
Htu2			
IOMM			
MibSpi1			
	GlbCtrl0	0x00000001	Global control register 0 [Memory Mapped]	
	GlbCtrl1	0x01000003	Global control register 1 [Memory Mapped]	
	Int0	0x00000158	Interrupt Register [Memory Mapped]	
	IntLvl	0x00000300	Interrupt Level Register [Memory Mapped]	
	IntFlg	0x00000300	Flag Register [Memory Mapped]	
	Fun	0x01010E17	Pin Control 0 [Memory Mapped]	
	Dir	0x00010617	Pin Control 1 [Memory Mapped]	
	DIn	0x0200023D	Pin Control 2 [Memory Mapped]	
	DOut	0x00000116	Pin Control 3 [Memory Mapped]	
	DSet	0x00000116	Pin Control 4 [Memory Mapped]	
	DClr	0x00000116	Pin Control 5 [Memory Mapped]	
	PDr	0x00000000	Pin Control 6 [Memory Mapped]	
	PDis	0x00000000	Pin Control 7 [Memory Mapped]	
	PSel	0x03030F3F	Pin Control 8 [Memory Mapped]	
	TxDat0	0x0000DA00	Transmit Data Register 0 [Memory Mapped]	
	TxDat1	0x103DDA00	Transmit Data Register 1 [Memory Mapped]	
	RxBuf	0x003D5555	Receive Buffer Register [Memory Mapped]	
	Emu	0x003D5555	Emulation Register [Memory Mapped]	
	Delay	0x00000000	Delay Register [Memory Mapped]	
	DefCs	0x0000003F	Default Chip select Register [Memory Mapped]	
	DatFmt0	0x00039F10	Data Format Register 0 [Memory Mapped]	
	DatFmt1	0x00000000	Data Format Register 1 [Memory Mapped]	
	DatFmt2	0x00000000	Data Format Register 2 [Memory Mapped]	
	DatFmt3	0x00000000	Data Format Register 3 [Memory Mapped]	
	TgIntVec0	0x00000000	Transfer Group Interrupt Vector Register 0 [Memory Mapped]	
	TgIntVec1	0x00000024	Transfer Group Interrupt Vector Register 1 [Memory Mapped]	
	SrSel	0x00000000	Pin Control Register 9 [Memory Mapped]	
	PmCtrl	0x00000000	Parallel/Modulo Mode Control Register [Memory Mapped]	
	MibSpiEna	0x00000000	MibSPI Enable Register [Memory Mapped]	
	TgIntEnaSet	0x00000000	MibSPI Transfer Group Interrupt Enable Set Register [Memory Mapped]	
	TgIntEnaClr	0x00000000	MibSPI Transfer Group Interrupt Enable Clear Register [Memory Mapped]	
	TgIntLvlSet	0x00000000	MibSPI Transfer Group Interrupt Level Set Register [Memory Mapped]	
	TgIntLvlClr	0x00000000	MibSPI Transfer Group Interrupt Level Clear Register [Memory Mapped]	
	TgIntFlg	0x00000000	Transfer Group Interrupt Flag Register [Memory Mapped]	
	TickCnt	0x00000000	Tick Cnt Register [Memory Mapped]	
	LTgPend	0x00000000	Last Transfer Group End Pointer [Memory Mapped]	
	Tg0Ctrl	0x00000000	MibSPI Transfer Group Control Register 0 [Memory Mapped]	
	Tg1Ctrl	0x00000000	MibSPI Transfer Group Control Register 1 [Memory Mapped]	
	Tg2Ctrl	0x00000000	MibSPI Transfer Group Control Register 2 [Memory Mapped]	
Spi2			
MibSpi3			
Spi4			
MibSpip5

Regards,
Usha Kumari