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TMS570LS2125's behavior under the pins short condition

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Other Parts Discussed in Thread: TMS570LS2125

Hello,

I have questions for the TMS570LS2125's (QFP package) behavior under the pins short condition.

1. #9 pin and #10 pin are shorted.
   #9 pin is N.C. externally. In internal, N2HET works as embedded clock and N2HET diagnostic.
   #10 pin is VCCIO = 3.3V.
   Could you teach me the impact in this case? Is the case no problem?

2. #34 pin and $35 pin are shorted.
   #34 pin is the TEST termination with the external pull-down (1kOhm) register.
   #35 pin is GIO. This GIO is in input mode and in High condition.
   Could you teach me the impact in this case? Is the state transition occurred into internal test mode?

3. #116 pin and #117 pin are shorted.
   #116 pin is N_RESET, drive = 4mA.
   #117 pin is N_ERROR, drive = 8mA.
   In past, I have questioned for same pin short condition in http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/235617/845305.aspx, however additional information is needed in the following conditions.
   - #116 pin is in High condition, and #117 pin is in Low condition.
   - #116 pin is in Low condition, and #117 pin is in High condition.
   Could you teach me the impact in these cases? And, are these pins tied to Low (N_ERROR=Low or N_RESET=Low)?
   I'm afraid of the bungle by medium electric potential.

Best Regards.

Nomoto

  • Nomoto-San,

    I will forward your question to our expert. He will be responding to your questions soon.

    Regards,

    QJ

  • Yusuke Nomoto said:

    Hello,

    I have questions for the TMS570LS2125's (QFP package) behavior under the pins short condition.

    1. #9 pin and #10 pin are shorted.
       #9 pin is N.C. externally. In internal, N2HET works as embedded clock and N2HET diagnostic.
       #10 pin is VCCIO = 3.3V.
       Could you teach me the impact in this case? Is the case no problem?

    HW: if #9 pin is not configured as output, I don't see any problem.

    2. #34 pin and $35 pin are shorted.
       #34 pin is the TEST termination with the external pull-down (1kOhm) register.
       #35 pin is GIO. This GIO is in input mode and in High condition.
       Could you teach me the impact in this case? Is the state transition occurred into internal test mode?

    HW: Test Mode is entered when TEST=1 and nTRST=1. So, because there are internal pull down on nTRST, if no external emulator connected, the device won't go to TEST mode. However, if TEST=1, the main clk (such the pll, osc...) will be gated, no clk to CPU. If the TEST pin recovers to '0' after some time(> ???ns, check datasheet), the nERROR pin will output low immediately indicating a Core Compare Error and a CCM R4 selftest error. If the "TEST=1" serves like a glitch less than ???ns (check the datasheet, different device has a different number here), "TEST=1" will be ignored. I recommend to tie TEST pin to ground on board.

    3. #116 pin and #117 pin are shorted.
       #116 pin is N_RESET, drive = 4mA.
       #117 pin is N_ERROR, drive = 8mA.
       In past, I have questioned for same pin short condition in http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/235617/845305.aspx, however additional information is needed in the following conditions.
       - #116 pin is in High condition, and #117 pin is in Low condition.

    HW: #116 is pull high 100uA (like 10Kohm), #117 is driving low (<10ohm), so it will be low.
       - #116 pin is in Low condition, and #117 pin is in High condition.

    HW: Both are are driving low/high. Driving low is usually stronger than driving high for the same buffer but 8mA buffer is stronger than 4mA, so the result is unknown.
       Could you teach me the impact in these cases? And, are these pins tied to Low (N_ERROR=Low or N_RESET=Low)?
       I'm afraid of the bungle by medium electric potential.

    Best Regards.

    Nomoto

  • Haixiao-san,

    Thank you for your reply.
    Now, I explain your answer to my customer.
    If my customer doesn't see any problem, I will close this thread.

    Best Regards

    Nomoto