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TMS570 Missing GIO pins

Andy Worsley
Intellectual 640 points
Other Parts Discussed in Thread: TMS570LS3135

I'm looking at the document SPNS164 - September 2011 for the TMS570LS3135.

In section 5.3 it says "The GPIO module on this device supports two ports, GIOA and GIOB.", but when I look at section 2.2 - the pinout for the 144 pin QFP device, I can only 4 pins labelled GIOA. Where did the rest of them go?

I'm guessing they're shared with another module, but how do I find out? Is there another document with more detail?

Thanks in anticipation

Andy

  • 0
    TI__Mastermind 22715 points

    Andy,

    Those are the only GIO module pins supported on the 144 pin QFP package. You need to use the ZWT package for full device functionality.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 640 points

    Zhaohong,

    I have 3 questions about this.

    The HET section reads "The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O.." How many of these pins can be used as IO?

    Are there any other modules that can be used as general purpose I/O, if so, which ones?

    The document I mentioned above doesn't go into the depth of what each register does. Which document does this?

    Regards

    Andy

  • 0 in reply to Zhaohong Zhang
    TI__Guru 65480 points

    Andy,

    In addition, most of the peripheral pins can be used as GPIO.   Most peripherals have the same set of DIR, DOUT, DIN, DSET, DCLR... etc registers for GIO that the GIO module does.

    So we tend to prioritize peripheral pins on smaller pkgs. because they can be used either as their peripheral function or as GIO.

    -Anthony

  • 0 in reply to Anthony F. Seely
    Intellectual 640 points

    Anthony,

    that's more reassuring that the device has more than 4 I/O pins!

    You said 'most' peripherals can be used as GPIO. I'm trying to allocate pins to specific functions, on a project where we're migrating from a microchip part to, hopefully, a TI part, but in order to show that this device can do the job, I need specifics. Isn't there a more detailed datasheet than the one I'm using?

    Thanks

    Andy

  • 0 in reply to Andy Worsley
    TI__Guru 65480 points

    Andy,

    We haven't put together a table unfortunately.   I can give you a brief summary.   You can double check by checking the register map of each peripheral in the TRM.

    The GIO registers are usually named   <per>PCx  where x is a #  or sometimes you see <per>DIR, <per>DIN, ... etc.

    These peripherals have GIO support:

        N2HET, GIO, DCAN, SCI, LIN, I2C, DMM, RTP,  ADC**

        ADC is **:  The ADC EVT pin has GIO capability.   The analog inputs can be converted and compared against a threshold register to produce a '1' or '0'.

    These do not support GIO:

       FlexRay, EMAC, MDIO, EMIF

    The other peripherals don't have IO.  I might have missed the odd peripeheral so if you see one I missed you can either check the TRM or post the specific question.

    Last note:  For some peripherals you can mix functions - use some peripheral pins for their function and some as GIO.   For example on N2HET you might only need 8 PWMs, the remaining pins can be used as GIO.   For SPI & MibSPI we have lots of chip selects and if you are not using these you can use them as GIO while still doing a basic 3 or 4 pin SPI with the other pins.   If you are going to do this however, please read the TRM chapter a bit more;  there might be certain minimal sets of pins needed as functional for the peripheral function itself.  For example, with SPI/MibSPI to get any SPI function you need SOMI, SIMO, and CLK configured as SPI ... the rest can be GIO or SPI function.   I think RTP and DMM have some discrete widths that they support as well for functional mode.

    -Anthony

     Edit: adding this point too...  we have pin muxing.  So if there is a pin that has both a GIO supporting and non-GIO supporting peripheral, you can use the pin as GIO by setting the pinmux to the peripheral that supports GIO.  Might be obvious but thought I should clarify.