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Initializing Watchdog on TM4C123BE6PZ

John Osen
Genius 3585 points

I am using CCS5.4 on a TM4C123BEPZ.  I am trying to initialize the watchdog timer.  My initialization code is:

void WDOG_Init(void) {
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0);

    WATCHDOG_TIMEOUT = SysCtlClockGet()/10;

    if(ROM_WatchdogLockState(WATCHDOG0_BASE) == true)
    {
        ROM_WatchdogUnlock(WATCHDOG0_BASE);
    }
    ROM_WatchdogStallEnable(WATCHDOG0_BASE);
    ROM_WatchdogIntClear(WATCHDOG0_BASE);
    ROM_WatchdogReloadSet(WATCHDOG0_BASE, WATCHDOG_TIMEOUT);
    ROM_IntEnable (INT_WATCHDOG);
    ROM_WatchdogEnable(WATCHDOG0_BASE);
}

I cannot get to the ROM_WatchdogEnable call.  As soon as I IntEnable, I end up in the watchdog ISR.

The code above is consistent with several StellarisWare examples.  There is not any applicable errata.  I have tried shuffling the order of the above code, to no avail.

Why am a getting an immediate interrupt when I enable the interrupt?

 

  • 0
    Guru 47900 points

    John Osen said:
    ROM_IntEnable (INT_WATCHDOG);

    Might (INT_WATCHDOG0) assist?

  • 0
    Genius 3585 points

    I have played with this a bit more.  The chip data sheet indicates the watchdog has a first vs. second countdown timer == 0 issue.  It seems that it is assumed the first interrupt is different from the second.  So I programmed the ISR such that the first time it just clears the interrupt flag and the second time (I do not set WatchdogResetEnable) I log the watchdog and system state, then I reset.

    So this almost seems like a feature.  I was wondering why some of the examples set WatchdogResetEnable, then in the ISR basically only reset the ISR flag. 

    After emulating the example's ISR behavior without setting WatchdogResetEnable, I am able to go into a forever loop and trigger the watchdog ISR a second time as I would expect.

    But, the data sheet indicates that the first ISR happens when the counter reaches zero.  I break before enabling the INT_WATCHDOG and the reset counter and actual counter are at expected values.  The masked and raw interrupt flags are clear.  I break at the first statement in the ISR and the counters are still at >> 0 values and both the raw and masked interrupt flags are set.  So the interrupt did not happen because the watchdog timer got to zero as the data sheet indicates.  It happens because the interrupt was enabled.

    What is the reasoning for this behavior?

  • 0 in reply to cb1
    Genius 3585 points

    I puzzled INT_WATCHDOG0 as well.  There appears to be only one watchdog ISR for this processor and it services both 0 and 1;  hence no numeral suffix to INT_WATCHDOG.  (I even tried to switch to using WATCHDOG1 and saw no change in results.)

    Thanks again for your time in consideration.