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TMS570 MibSPI multi-buffer mode interacting with an A/D converter

Other Parts Discussed in Thread: TMS570LS2134

Hi experts,

I'm looking to use an integrated TMS570 MibSPI to communicate with an Analog Devices AD7490 SPI ADC (16 channels).The included documentation in the spnu499a doesn't provide enough information for my understanding of how the MibSPI multi-buffer mode works.

Here is the situation: the AD7490 ADC has the ability, after been programmed, to perform continuous conversions on dummy input clock pulses, 16 SPI clock pulses per channel. For my purpose, on each reading cycle, I have 18 x 16-bit words to transmit over to the external ADC (1x dummy write, 1x configuration word and 16x dummy write to read). Starting with the third transmission, I'll have valid conversion result for the first analog input channel coming back from the ADC.

Here is what I want to achieve:

1) Configure the TMS570LS2134 MibSPI1 in multi-buffer master mode (ADC in slave mode)

2) Store the 18 x 16-bit words for TX in one TX buffer memory

3) Use the selected N2HET1 pin (EVENTs 8 ... 13) that will be triggered with a fixed timer interrupt, to start the TX/RX cycle on a timely fashion, by transmitting the 18x predefined words on the SPI (DMA???)

4) All without CPU intervention, while the SPI is TX, read and store RX results in another RX buffer memory (DMA???)

5) When last 16 bits are stored in the RX buffer memory, interrupt the CPU of its completion

Is this something feasible with the TMS570?

If so, what registers should I use and how the DMA and TG are involved?

Thank you for any help.


  • Hi Chuck,

    Can you pls refer to the below thread to see if you get some sample projects with MIBSPI DMA.

    Best Regards,


  • Sorry for the long delay before coming back to this post. I have been assigned on other projects lately.

    And no I didn't find anything that can actually lead me to understand clearly how the MibSPI, when configured in multi-buffer mode, is working with Transfer Group and handshake with DMA. I need to understand well how the MCU MibSPI/DMA process interaction is working before can actually attempt to read source code examples.

    I need to configure the MibSPI1 in master mode and multi-buffer mode to transfer a group of 24x 16-bit data words (with fix contents) that are stored in the MibSPI1 TXRAM, starting as Transfer Group #1 at buffer 2 and ending at buffer 25. At the end of the transfer, I need to read back the 24-word data buffer from the corresponding RXRAM.

    Let's see whether my understanding of the MCU MibSPI/DMA process interaction is correct.

    1. I configure basic MibSPI1 registers accordingly with data format and modes of operation.
    2. I configure TG1CTRL0 as required for another TG to use buffer locations 0 and 1.
    3. I configure TG1CTRL1 for this subject as follow:
    • ONESHOT=1: I'll manually re-enable TGENA bit after each RXRAM read
    • PSTART=2: Starting at buffer 2
    • TRIGEVT=1: Triggered on rising edge
    • TRIGSRC=1011b: Set N2HET1[12] as trigger source
    1. I configure TG1CTRL2 to start from buffer 26. I configure TG1LTGPEND to buffer 127.
    2. I configure the 24-word buffer and write data to the TXRAM, starting at buffer location 2, for cyclic transmission over SPI1, with BUFMODE=6: Suspend overwrite-protect mode (TX data are fix and will not be update, and do not over-write RX data).
    3. I configure MibSPI1DMA0CTRL as follow:
    • ONESHOT=0: Let DMA to control block transfer
    • BUFID=25: To enable RXDMA when the transfer of TG0 is done
    • RXDMA_MAP=2: MibSPI to DMA request channel for 24-word data reading
    • TXDMA_MAP=1: MibSPI to DMA request channel for 24-word data transmitting
    1. I configure DMA channel X (corresponding to MibSPI request 1) to write 24 words from TXRAM with ELEMENT=24, FRAME=1.
    2. I configure DMA channel Y (corresponding to MibSPI request 2) to read 24 words from RXRAM once RXDMA is triggered by MibSPI1 with ELEMENT=24, FRAME=1.
    3. I then enable RXDMAENA and TXDMAENA in MibSPI1DMA0CTRL.
    4. Every time when the rising edge on N2HET1[12] is detected, 24 words will be written successively to SPI1, spaced and controlled by the MibSPI1 sequencer, and the same number will be read from the RXRAM at the end of transmission. I then need to re-enable TGENA=1 to get ready for the next hardware trigger from N2HET1[12].

    Does this sequence sound good? Is there anything missing?

    Will the writing to SPI1 transmission buffer be correctly controlled by the MibSPI sequencer event the DMA channel ELEMENT=24 and FRAME=1?

    Many thanks for a quick reply.

  • Alright, So I will attempt to answer my own question since finally, I think that I understood how the MibSPI sequencer, TXDMA and RXDMA work. Hopefully this can help others as the info in the TRM are not really properly put up together for easy understanding.

    I was initially thinking that the TXDMA is the DMA used to transfer data words from the TXRAM to the SPIDAT1 register. But it isn't! Actually:

    • The TXDMA is used to transfer data from SW application RAM to SPI TXRAM.
    • The RXDMA is used to transfer data from SPI RXRAM to SW application RAM.
    • The MibSPI sequencer is used to transfer data from TXRAM to SPIDAT1 register and to synchronize the SPI transmission with BUFMODE setting, until TX of TG is completed (last TG data word transferred).

    After "correctly" understood those facts, everything else seems make sens now. So this is what will happen for the scenario in my second post of this thread. Please correct me if I'm still wrong.

    1. During power-up initialization, the SW application writes 24 words with fix contents to the TXRAM. The TXRAM data will not be modified thereafter. Therefore the TXDMA does not need to be enabled to update this TXRAM.
    2. Configure the DMA channel responding to RXDMA to copy 1 frame of 24 elements from RXRAM to SW application RAM buffer on each request, and to generate an END_OF_DMA_TRANSFER interrupt.
    3. When TG1 is triggered on a rising edge of N2HET1[12], the MibSPI1 sequencer sends the first TXRAM word, identified by TG1CTRL1->PSTART=2, to the SPI1DAT1 register.
    4. SPI1 then serially shifts out the 16-bit word on SIMO, after which the MibSPI1 sequencer sends the next TXRAM word. This process continues until the MibSPI1 sequencer sends out the last TXRAM word in location TG1CTRL2->PSTART‑1=25.
    5. The MibSPI1 sequencer then stops by clearing TG1CTRL1->TGENA=0.
    6. Since the MibSPI1DMA0CTRL->BUFID=25 was configured, upon the receiving of the last data in TG1’s RXRAM buffer location 25, a RXDMA will be generated to instruct the DMA controller to copy all 24 RX words to the SW application RAM.
    7. Set TG1CTRL1->TGENA to 1 again to start TG upon next N2HET1[12] trigger rising edge.

    I still have to test it out on the real setup though ...

    If the above is correct, I think that putting something like this in the TRM will certainly help people. Hopefully this will help others in need.