Hi to everybody.
I'm facing a problem with a TMS470MF03107 (CORTEX M3) about the SYSRESETREQ bit.
In order to stop the core in debug state I follow this procedure (that I used succesfully for many other cortex M3 device, as Stellaris LM3S3739):
1. setting of C_DEBUGEN, C_HALT and C_MASKINTS in the Debug Halting Control and Status Register
2. waiting for the S_HALT bit to be set
3. write to the the Application Interrupt and Reset Control Register in order to set the SYSRESETREQ
4. Wait a complete transition 0-1-0 of the S_RESET_ST bit
5. enter debug state on reset, setting VC_CORERESET in the Debug Exception and Monitor Control Register
6. request a reset, setting the VECTCLRACTIVE and VECTRESET bits in the Application Interrupt and Reset Control Register
7. Wait a complete transition 0-1-0 of the S_RESET_ST bit
8. write 0xffffffff to the DFSR
9. disable the vector catching writing 0 to DEMCR register.
I'm facing the issue at point 3. When I read the Application Interrupt and Reset Control Register it results that the write has not take effect and subsequently at point 4 the S_RESET_ST bit results always zero.
It seems that no system reset has taken effect
Can anyone help me? Should I modify the procedure to work with TMS470M?
Thanks in advance for your prompt replies
Best regards
Stefano