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TMS570LS2134 SPI4 and MibSPI5 chip-select

Other Parts Discussed in Thread: TMS570LS2134

Hi there,

Might be a dumb question ... on the PGE 144-pin package TMS570LS2134 MCU, the SPI4 and MibSPI5 each has only one single chip-select signal (CS0), and I need to use one of them to address two external SPI devices.

Can your expert tell me whether it is possible to add some glue logics to share the single CS0 line for two external SPI devices (i.e. CS0 connected to one device and /CS0 using external inverter connected to the other one)?

In other words, is it possible for the internal SPI4/MibSPI5 to clock in/out data when the CS0 signal is commanded to be HIGH while writing to the DAT0/DAT1 registers?


  • Hello,

    Your proposal could work but I don't think it's the best approach. If you use only one CS line and an inverter to communicate with 2 devices you would need to constantly change the polarity of the CS line and also one of the devices will always be on communication mode.

    If definitively you can't use 2 different SPI instances I would recommend to use an I/O as your additional CS line and handle it before and after every SPI communication



  • Hi Enrique,

    That would make lot of sense.

    Do you mean to use the in-peripheral CS to control one SPI and one additional I/O to control the second one?

    Does this imply that when writing to the DAT0/DAT1 register in SPI compatibility mode with CS=HIGH, the data will be correctly clocked out the SDO pin, with its CS line set to HIGH?


  • Hello:

    If you use SPIDAT1 register to transmit data you can control which CS pin in handled (or no CS handled at all) in CSNR. If you are trying to communicate with the device connected to the CS line, you can set it there. If you are trying to communicate with the device connected to the I/O you need to keep the inactive value of your CS pin in CSNR.



  • Sorry to reopen this case, need your help on the TMS570LS2134PGE package.

    I need to use the MibSPI1 and MibSPI3 in multi-buffer mode. On page 1332 of the spnu499a TRM, for CSNR field, it states on Note 2 that "Bits [23:20] is not writable in the device due to non availability of Chip select pins CS[4:7]", while on page 16 of the spns165a datasheet, for instance in the 144PGE package, MIBSPI1NCS[4] and MIBSPI1NCS[5] are shared with N2HET1[15] and N2HET1[24] respectively.

    My questions are:

    Can one configure those shared pins to use as MibSPI chip-select?

    If so, which register need to be configured to select the pins for one device rather than for the other?

    Otherwise, what is the purpose to list those pins in the datasheet?

    Many thanks!

  • Wondering anyone on this old thread?