This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS1225 Thumb / Arm mode help

Other Parts Discussed in Thread: TMS570LS1225

We observed a crash today in the following code.



00028240:   E92D4004 STMFD           R13!, {R2, R14}

00028244:   E1B02001 MOVS            R2, R1

00028248:   0A00000B BEQ             div_by_zero

0002824c:   E28FE001 ADD             R14, PC, #1

00028250:   E12FFF1E BX              R14

00028254:   FBB0FEF1 UDIV.W          R14, R0, R1

00028258:   4778     BX              PC

0002825a:   BF00     NOP

0002825c:   E002019E MUL             R2, R14, R1


An ISR occurred and its return address was 0x28258. It appears that the processor is in Thumb mode when we entered the interrupt. However when the ISR returned it appears that the statements at 0x2825C was never executed because R2 still has the function entrance value. Any ideas? Are there any ISR rules that we must follow when operating with both Thumb and Arm mode?

  • Dan, on the TMS570LS1225, the CPU will change to ARM mode on an interrupt. The C-compiler allows interrupt routines to be Thumb mode, so make sure your interrupt handler is in ARM mode. It should return to the proper mode at the end of the interrupt routine.
  • Dan,
    If using nested interrupts be sure to do a context save of all necessary registers including CPSR and banked registers. CPSR T bit will switch between thumb and arm mode. If this isn't saved and restored it's possible to return in the incorrect mode and get various exceptions.

    Forum Support