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LM3S3748 changed pin definition

Jusitn Anderson
Prodigy 140 points
Other Parts Discussed in Thread: LM3S3748, EK-LM3S3748

Greetings,

I'm modifying a legacy software application with an LM3S3748 Stellaris processor.  There was an issue with tool archival and only the 'source' directory has been preserved.  Tools and other directories are gone.

I've installed the latest version of Code Composer Studio (6.1.1.00022; compiler 5.2.5, 5.1.14, 15.12.2 ), along with  SW-DRL-10636 and SW-USBL-10636.  The 'SW' packages have resolved the missing dependencies (at least what I see for the moment).

The issue I'm wrestling with is apparently the pin definitions have changed.  There is now a pin_map.h that is also used with hw_gpio.h.  This is fine, however specific definitions are not present.

Example:

GPIO_PA5_SSI0TX - MISSING

However, the below are present

#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA

#define SSI0TX_PORT             GPIO_PORTA_BASE

#define SSI0TX_PIN             GPIO_PIN_5

Does anyone know where to find the original 'h' file that contained the definitions?

Curiously, the definitions are available for other parts, but not the LM3S3748 (ex.LM3S9G97)

Alternatively, suggestions on modification of the pins to match the definitions?  Certainly reading the datasheet and reviewing the schematic, I can manually set these up, but I'm hoping to limit the regression testing needed (still have not made the required changes yet).

Missing items:

identifier "GPIO_PE3_SSI1TX" is undefined 

identifier "GPIO_PE2_SSI1RX" is undefined

identifier "GPIO_PE1_SSI1FSS" is undefined 

identifier "GPIO_PE0_SSI1CLK" is undefined 

identifier "GPIO_PA5_SSI0TX" is undefined 

identifier "GPIO_PA4_SSI0RX" is undefined

identifier "GPIO_PA3_SSI0FSS" is undefined

identifier "GPIO_PA2_SSI0CLK" is undefined

Any assistance would be greatly appreciated.

 

Regards

JMA

  • 0
    TI__Guru**** 244380 points
    Hello Justin,

    I checked StellarisWare and there some LM3S device which do not have the new defines to be used with GPIOPinConfigure. You would need to check the pin maps and create those defines

    Regards
    Amit
  • 0
    Prodigy 140 points
    Greetings,
     
    Thank you for the response.  Please answer my other question, if the original file can be provided.  Thank you.
     
     
    Justin Anderson
    Senior Project Engineer
    847.505.1270 OFFICE
     
     
               
    2383 N Delany Rd    Waukegan, IL 60087
    847.662.6260 MAIN   www.tecnova.com
     
    CONFIDENTIAL NOTICE - This email and any files transmitted with it may contain PRIVILEGED or CONFIDENTIAL information and may be read or used only by
    the intended recipient.  If you have received this email in error, please notify the sender immediately by reply email and delete this email and all attachments.
     
  • 0 in reply to Jusitn Anderson
    TI__Guru**** 244380 points
    Hello Justin,

    Can you check the package "SW-LM3S-LM4F: Legacy StellarisWare® for LM3S and LM4F MCUs – September 2012 Release (v9453)" from the following link

    http://www.ti.com/tool/sw-lm3s

    Regards
    Amit
  • 0
    Prodigy 140 points
    Greetings,
     
    Thank you for the suggestion.  However, I downloaded and searched the directories, but the definitions in question are not present.  Any ideas?
     
    Is it possible for you to provide an example of how to setup the multiplexed port for SSI0 on the LM3S3748?
     
             // examine for setting up this configuration?
            //  The examples I can find only show the trivial case using the method that is below and for some reason this
           //    is no longer available and the file listing these definitions cannot be found
        GPIOPinConfigure(GPIO_PA2_SSI0CLK);                       /* Set PA2 as SSI0 Clock */
        GPIOPinConfigure(GPIO_PA3_SSI0FSS);                       /* Set PA3 as SSI0 NSS */
        GPIOPinConfigure(GPIO_PA4_SSI0RX);                        /* Set PA4 as SSI0 Rx */
        GPIOPinConfigure(GPIO_PA5_SSI0TX);                        /* Set PA5 as SSI0 Tx */
           
     
        // This should be fine for portA SSI0 pins 28 – 31 on LQFP;
        GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
                       GPIO_PIN_2);                                      /* Set Port A pins mode */
     
    Thank you for your time.
     
     
    Best Regards,
    Justin Anderson
    Senior Project Engineer
    847.505.1270 OFFICE
     
     
               
    2383 N Delany Rd    Waukegan, IL 60087
    847.662.6260 MAIN   www.tecnova.com
     
    CONFIDENTIAL NOTICE - This email and any files transmitted with it may contain PRIVILEGED or CONFIDENTIAL information and may be read or used only by
    the intended recipient.  If you have received this email in error, please notify the sender immediately by reply email and delete this email and all attachments.
     
  • 0 in reply to Jusitn Anderson
    TI__Guru**** 244380 points
    Hello Justin,

    The GPIOPinConfigure is not supported function for this class of devices

    Regards
    Amit
  • 0
    Prodigy 140 points
    Greetings,
     
    Interesting response.  With working firmware I tend to disagree with you, but I do not have ever single piece of ‘source’ that went into the build (evidenced by my questions).
     
     
    Either way, please illustrate an example with setting up the SSI0 on an LM3S3748 that does not support GPIOPinConfigure( ).  All the examples I’ve come across show the GPIOPinConfigure() method.  Thank you in advance.
     
     
    Step 1: configure pins
     
    Step 2:
    Setup SSI
        GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
                       GPIO_PIN_2);                                     
     
    Regards,
    Justin Anderson
    Senior Project Engineer
    847.505.1270 OFFICE
     
     
               
    2383 N Delany Rd    Waukegan, IL 60087
    847.662.6260 MAIN   www.tecnova.com
     
    CONFIDENTIAL NOTICE - This email and any files transmitted with it may contain PRIVILEGED or CONFIDENTIAL information and may be read or used only by
    the intended recipient.  If you have received this email in error, please notify the sender immediately by reply email and delete this email and all attachments.
     
  • 0 in reply to Jusitn Anderson
    TI__Guru**** 244380 points
    Hello Justin,

    I was looking at the comments for the lines GPIOPinConfigure which state that

    //! The available mappings are supplied on a per-device basis in
    //! <tt>pin_map.h</tt>. The \b PART_IS_<partno> define enables the
    //! appropriate set of defines for the device that is being used.
    //!
    //! \note This function is not valid on Sandstorm, Fury, and Dustdevil-class
    //! devices. Also, if the same signal is assigned to two different GPIO port
    //! pins, the signal is assigned to the port with the lowest letter and the
    //! assignment to the higher letter port is ignored.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 47900 points
    Hi Amit,

    As a fellow user - like poster Justin - I can confirm that (you, Amit) are absolutely correct. My firm has employed several K of "Dust Devil" devices - and that "GPIOPinConfigure()" is not valid for (our) Dust Devil devices.

    I'm uncertain of poster's device class - I recall that "Sandstorm" were earliest LM3S devices, Dust Devil & Fury later - and the problematic "Tempest" arrived last.

    I note that our small firm has long used Stellaris 9453 as the (last) version of StellarisWare able to support our LM3S & LX4F MCUs.
  • 0
    Prodigy 140 points
    Greetings,
     
    Thank you Amit and cb1.  This is certainly a mystery on my end.  Any chance this feature was implemented and being used prior to TI purchasing Luminary Micro (Stellaris) in 2009?
     
     
    If possible, please provide an example setting up SSI0 as requested.  All of the examples us the GPIOPinConfigure that I have come across.  A clear example will get me started in the right direction.  Thank you.
     
     
    Best Regards,
    Justin Anderson
    Senior Project Engineer
    847.505.1270 OFFICE
     
     
               
    2383 N Delany Rd    Waukegan, IL 60087
    847.662.6260 MAIN   www.tecnova.com
     
    CONFIDENTIAL NOTICE - This email and any files transmitted with it may contain PRIVILEGED or CONFIDENTIAL information and may be read or used only by
    the intended recipient.  If you have received this email in error, please notify the sender immediately by reply email and delete this email and all attachments.
     
  • 0 in reply to Jusitn Anderson
    Guru 47900 points

    Would you be so good as to check & report the "class" of your MCU.    If it is a "Dust Devil" I can code up our Dust Devil - and report.

    We also have the first Stellaris (Sandstorm) - these were 28 pin soic devices - promised @ 1 (USD) in volume.  (a promise - btw - unkept)

  • 0 in reply to Jusitn Anderson
    TI__Guru**** 244380 points
    Hello Justin

    I do see some examples for ek-lm3s3748 devices, but since I am not familiar with this particular device, my bets bet would be to investigate the example codes. I would need some time to go through the pin configuration on this device

    Regards
    Amit
  • 0
    Prodigy 140 points
    Greetings,
     
    The LM3S3748 apparently is a dust devil class device.  Any assistance or example with SSIO (SPI) would be greatly appreciated.  Thank you.
     
     
     
     
    Best regards,
    Justin Anderson
    Senior Project Engineer
    847.505.1270 OFFICE
     
     
               
    2383 N Delany Rd    Waukegan, IL 60087
    847.662.6260 MAIN   www.tecnova.com
     
    CONFIDENTIAL NOTICE - This email and any files transmitted with it may contain PRIVILEGED or CONFIDENTIAL information and may be read or used only by
    the intended recipient.  If you have received this email in error, please notify the sender immediately by reply email and delete this email and all attachments.
     
  • 0 in reply to Jusitn Anderson
    Guru 47900 points
    OK then - we have several hundred LM3S16xx remaining - also Dust Devil. Tomorrow we'll code up and report here in your behalf.
  • 0 in reply to cb1
    TI__Guru**** 244380 points
    Hello cb1

    Thank you for helping us out (Note that DustDevil precedes me)

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 47900 points
    We note that "Dust Devil" precedes Tyrannosaurus Rex, too. (only we LMI "originals" roamed the earth during that bygone era...)
  • 0 in reply to cb1
    Guru 117850 points

    Follows "known good" SPI set-up code which operates well w/past (departed) LM3S Dust Devil devices:

    SPI_LMI.txt 
    	// The GPIO port A pin numbers for the various SSI signals.
	//
	#define SSI_CS                  GPIO_PIN_3
	#define SSI_CLK                 GPIO_PIN_2
	#define SSI_TX                  GPIO_PIN_5
	#define SSI_RX                  GPIO_PIN_4

    // Set the clocking to run directly from the crystal.
    //
    SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |
                   SYSCTL_XTAL_6MHZ);

    // Enable the peripherals used by this example.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

    // Configure the appropriate pins to be SSI instead of GPIO.  Note that
    // the chip select is kept as a GPIO to guarantee the appropriate
    // signalling to the Atmel device.
    //
    GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, SSI_CS);
    GPIOPinWrite(GPIO_PORTA_BASE, SSI_CS, SSI_CS);
    GPIOPinTypeSSI(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX);

    //
    // Configure and enable the SSI port for master mode.
    //
    SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
                       SSI_MODE_MASTER, 1000000, 16);
    SSIEnable(SSI0_BASE);

    Note that "no" (more modern) "GPIOPinConfigure()" calls appear w/this vintage MCU.

  • 0
    Prodigy 140 points
    Greetings cb1,
     
    Thank you, much appreciated.
     
     
    Justin Anderson
    Senior Project Engineer
    847.505.1270 OFFICE
     
     
               
    2383 N Delany Rd    Waukegan, IL 60087
    847.662.6260 MAIN   www.tecnova.com
     
    CONFIDENTIAL NOTICE - This email and any files transmitted with it may contain PRIVILEGED or CONFIDENTIAL information and may be read or used only by
    the intended recipient.  If you have received this email in error, please notify the sender immediately by reply email and delete this email and all attachments.
     
  • 0 in reply to Jusitn Anderson
    Guru 117850 points
    Thank you for your prompt acknowledgement, Justin.
    One of our warehouses has at least 10-20 of your device - and perhaps few hundred (mix - n total) of these "orphaned" LM3S MCUs