Hello All,
I'm using the SPI5 on a TMS570LS20216-EP to send three bytes to an SPI DAC.
I set the bytes with an 'spiSetData' then initiate the transfer with 'spiTransfer'.
What I see on the chip select line and clock is a transfer of three bytes, but inbetween each byte the chip select briefly returns high. I was expecting to see the chip select low for the three byte transfer.
I've attached a scope capture that shows the chip select line and clock.
The initialisation code for SPI5 is also shown below.
Am I doing anything wrong in my initialisation?
/** bring SPI out of reset */
spiREG5->GCR0 = 1U;
/** enable SPI5 multibuffered mode and enable buffer RAM */
spiREG5->MIBSPIE = (spiREG5->MIBSPIE & 0xFFFFFFFEU) | 1U;
/** SPI5 master mode and clock configuration */
spiREG5->GCR1 = (spiREG5->GCR1 & 0xFFFFFFFCU) | ((1U << 1U) /* CLOKMOD */
| 1U); /* MASTER */
/** SPI5 enable pin configuration */
spiREG5->INT0 = (spiREG5->INT0 & 0xFEFFFFFFU) |(0U << 24U); /* ENABLE HIGHZ */
/** - Delays */
spiREG5->DELAY = (1U << 24U) /* C2TDELAY */
| (1U << 16U) /* T2CDELAY */
| (0U << 8U) /* T2EDELAY */
| 0U; /* C2EDELAY */
/** - Data Format 0 */
spiREG5->FMT0 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 1 */
spiREG5->FMT1 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 2 */
spiREG5->FMT2 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 3 */
spiREG5->FMT3 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - wait for buffer initialization complete before accessing MibSPI registers */
while ((spiREG5->FLG & 0x01000000U) != 0U)
{
} /* Wait */
/** - initialize transfer groups */
spiREG5->TGCTRL[0U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| (0U << 8U); /* start buffer */
spiREG5->TGCTRL[1U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| (3U << 8U); /* start buffer */
spiREG5->TGCTRL[2U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[3U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[4U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[5U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[6U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[7U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[8U] = (3U+0U+0U+0U+0U+0U+0U+0U) << 8U;
spiREG5->LTGPEND = (spiREG5->LTGPEND & 0xFFFF00FFU) | (((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
/** - initialize buffer ram */
{ i = 0U;
if (8U > 0U)
{
while (i < (8U-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_0; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_0; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_1; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_1; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_2; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_2; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_3; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_3; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_4; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_4; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_5; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_5; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_6; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_6; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
}
/** - set interrupt levels */
spiREG5->LVL = (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */
/** - clear any pending interrupts */
spiREG5->FLG |= 0xFFFFU;
/** - enable interrupts */
spiREG5->INT0 = (spiREG5->INT0 & 0xFFFF0000U)
| (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */
/** @b initialize @b SPI5 @b Port */
/** - SPI5 Port output values */
spiREG5->PCDOUT = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI5 Port direction */
spiREG5->PCDIR = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI5 Port open drain enable */
spiREG5->PCPDR = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI5 Port pullup / pulldown selection */
spiREG5->PCPSL = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */
/** - SPI5 Port pullup / pulldown enable*/
spiREG5->PCDIS = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/* SPI5 set all pins to functional */
spiREG5->PCFUN = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */
/** - Finally start SPI5 */
spiREG5->GCR1 = (spiREG5->GCR1 & 0xFEFFFFFFU) | (1U << 24U);
/** bring SPI out of reset */
spiREG5->GCR0 = 1U;
/** enable SPI5 multibuffered mode and enable buffer RAM */
spiREG5->MIBSPIE = (spiREG5->MIBSPIE & 0xFFFFFFFEU) | 1U;
/** SPI5 master mode and clock configuration */
spiREG5->GCR1 = (spiREG5->GCR1 & 0xFFFFFFFCU) | ((1U << 1U) /* CLOKMOD */
| 1U); /* MASTER */
/** SPI5 enable pin configuration */
spiREG5->INT0 = (spiREG5->INT0 & 0xFEFFFFFFU) |(0U << 24U); /* ENABLE HIGHZ */
/** - Delays */
spiREG5->DELAY = (1U << 24U) /* C2TDELAY */
| (1U << 16U) /* T2CDELAY */
| (0U << 8U) /* T2EDELAY */
| 0U; /* C2EDELAY */
/** - Data Format 0 */
spiREG5->FMT0 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 1 */
spiREG5->FMT1 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 2 */
spiREG5->FMT2 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - Data Format 3 */
spiREG5->FMT3 = (0U << 24U) /* wdelay */
| (0U << 23U) /* parity Polarity */
| (0U << 22U) /* parity enable */
| (0U << 21U) /* wait on enable */
| (0U << 20U) /* shift direction */
| (0U << 17U) /* clock polarity */
| (0U << 16U) /* clock phase */
| (79U << 8U) /* baudrate prescale */
| 16U; /* data word length */
/** - wait for buffer initialization complete before accessing MibSPI registers */
while ((spiREG5->FLG & 0x01000000U) != 0U)
{
} /* Wait */
/** - initialize transfer groups */
spiREG5->TGCTRL[0U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| (0U << 8U); /* start buffer */
spiREG5->TGCTRL[1U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| (3U << 8U); /* start buffer */
spiREG5->TGCTRL[2U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[3U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[4U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[5U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[6U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[7U] = (1U << 30U) /* oneshot */
| (0U << 29U) /* pcurrent reset */
| (TRG_ALWAYS << 20U) /* trigger event */
| (TRG_DISABLED << 16U) /* trigger source */
| ((3U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
spiREG5->TGCTRL[8U] = (3U+0U+0U+0U+0U+0U+0U+0U) << 8U;
spiREG5->LTGPEND = (spiREG5->LTGPEND & 0xFFFF00FFU) | (((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
/** - initialize buffer ram */
{ i = 0U;
if (8U > 0U)
{
while (i < (8U-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_0; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_0; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_1; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_1; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_2; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_2; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_3; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_3; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_4; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_4; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_5; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_5; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_6; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_6; /* chip select */
}
if (0U > 0U)
{
while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U))
{
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (1 << 12) /* hold chip select */
| (0U << 11U) /* lock transmission */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
spiRAM5->tx[i++].control = (4U << 13U) /* buffer mode */
| (0U << 12U) /* chip select hold */
| (0U << 10U) /* enable WDELAY */
| (0U << 8U) /* data format */
| CS_7; /* chip select */
}
}
/** - set interrupt levels */
spiREG5->LVL = (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */
/** - clear any pending interrupts */
spiREG5->FLG |= 0xFFFFU;
/** - enable interrupts */
spiREG5->INT0 = (spiREG5->INT0 & 0xFFFF0000U)
| (0U << 9U) /* TXINT */
| (0U << 8U) /* RXINT */
| (0U << 6U) /* OVRNINT */
| (0U << 4U) /* BITERR */
| (0U << 3U) /* DESYNC */
| (0U << 2U) /* PARERR */
| (0U << 1U) /* TIMEOUT */
| (0U); /* DLENERR */
/** @b initialize @b SPI5 @b Port */
/** - SPI5 Port output values */
spiREG5->PCDOUT = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI5 Port direction */
spiREG5->PCDIR = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI5 Port open drain enable */
spiREG5->PCPDR = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/** - SPI5 Port pullup / pulldown selection */
spiREG5->PCPSL = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */
/** - SPI5 Port pullup / pulldown enable*/
spiREG5->PCDIS = 0U /* SCS[0] */
| (0U << 1U) /* SCS[1] */
| (0U << 2U) /* SCS[2] */
| (0U << 3U) /* SCS[3] */
| (0U << 8U) /* ENA */
| (0U << 9U) /* CLK */
| (0U << 10U) /* SIMO */
| (0U << 11U); /* SOMI */
/* SPI5 set all pins to functional */
spiREG5->PCFUN = 1U /* SCS[0] */
| (1U << 1U) /* SCS[1] */
| (1U << 2U) /* SCS[2] */
| (1U << 3U) /* SCS[3] */
| (1U << 8U) /* ENA */
| (1U << 9U) /* CLK */
| (1U << 10U) /* SIMO */
| (1U << 11U); /* SOMI */
/** - Finally start SPI5 */
spiREG5->GCR1 = (spiREG5->GCR1 & 0xFEFFFFFFU) | (1U << 24U);
