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TMS570LS3134: Questions for Errata ADC#1

Part Number: TMS570LS3134


I got two questions from customer regarding Errata ADC#1.

1) The workaround#2 says “Configure the two ADC modules such that their sampling periods do not overlap”.
Is there any timing gap required between these back to back sampling periods?
(ex. XX usec or YY cycles of ADCLK)
Or next sampling can be started as soon as previous one is finished ?
2) In two workaround options, which one will be more effective ?
I guess #1. And #2 is second option in case #1 cannot be used.

Thanks and regards,

  • Hi KoT,

    The two workarounds are for the following 2 conditions which cause the issue:

         1. Input voltage on a shared input channel being sampled by one ADC is (VCCAD - 0.3V) or higher, and

         2. The second ADC samples another channel such that there is some overlap between the sampling windows of the two ADCs

    You can use either workaround #1 or #2. There is no preference.

    The timing gap is not defined and required between 2 consecutive sampling windows of 2 ADCs



  • Hi QJ,

    Thanks for your answer and sorry for my late reply

    My customer wants to use the 2nd workaround as they want to use ADC1 and ADC2 simultaneously.
    Errata says “The PMOS leakage is reduced exponentially if the input is lower than VCCAD-0,3V”.

    Do we have any data available showing voltage and error dependency? (under either condition is fine)
    Customer wants to estimate how much they need to reduce analog input voltage.

    Thanks and regards,

  • Hi QJ,

    Could you reply this ?

    Thanks and regards,