I got two questions from customer regarding Errata ADC#1.
1) The workaround#2 says “Configure the two ADC modules such that their sampling periods do not overlap”.
Is there any timing gap required between these back to back sampling periods?
(ex. XX usec or YY cycles of ADCLK)
Or next sampling can be started as soon as previous one is finished ?
2) In two workaround options, which one will be more effective ?
I guess #1. And #2 is second option in case #1 cannot be used.
Thanks and regards,