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TM4C123AH6PM: tm4c

Norbert Toth
Expert 1145 points
Part Number: TM4C123AH6PM

Hi Folks,

I think, my querstion is not exactly belongs to the part number singed in the post, but it can be present most of the TM4C processors.

I have to implement H bridge drive. As the datasheet also mentioned, a dead-band time is required to turn OFF the active pair before the opposite one will turn ON,

My question is, what is the exact behavior, when the duty cycle is smaller than the dead-band time? Will the comparator events be "ignored"? How can I image these situtation?

(I mean "these" as this situation can be appear if the dutiy cycle is smaller that the dead-band time, or their sum is greather than the period time)

Regards,

Norbert

  • 0
    Guru 117850 points
    As the dead-band forces signal width limitations upon (potentially) both the leading & trailing edge of the lower order PWM output (w/in that particular PWM Generator) it appears that the duty cycle will approach (and decline) to zero.

    Without benefit (or more likely any harmful effects introduced by a "real" load) you could easily scope both outputs of a programmed PWM Generator - and experiment to confirm results - on your actual MCU & board...

    I past placed scope captures (this forum) showing the exact "restrictions in signal width - imposed upon the lower order PWM Generator output signal - when operating under dead-band."